ADSP-BF592KCPZ Analog Devices Inc, ADSP-BF592KCPZ Datasheet - Page 23

• Manufacturer Part Number: ADSP-BF592KCPZ
• Description: 58T4522
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF592KCPZ

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Rohs Compliant: YES
• Frequency: 400MHz
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 32
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Core Supply Voltage: 1.4V
• Lead Free Status / RoHS Status: Compliant

Preliminary Technical Data
Table 19. Package Brand Information
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Clock and Reset Timing
Table 20
the CCLK and SCLK timing specifications in
Table
not select core/peripheral clocks in excess of the processor’s
instruction rate.
Table 20. Clock and Reset Timing
1
2
3
4
5
Brand Key
ADSP-BF592
t
pp
Z
ccc
vvvvvv.x
n.n
#
yyww
Parameter
Timing Requirements
f
t
t
t
Switching Characteristic
t
Applies to PLL bypass mode and PLL non bypass mode.
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
The t
If the DF bit in the PLL_CTL register is set, the minimum f
Applies after power-up sequence is complete. See
CKIN
CKINL
CKINH
WRST
BUFDLAY
Table 12 on Page
CKIN
12, combinations of CLKIN and clock multipliers must
period (see
and
Figure 7
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulse Width Low
CLKIN to CLKBUF Delay
19.
Figure
describe clock and reset operations. Per
7) equals 1/f
1, 2
Product Name
Temperature Range
Package Type
See Ordering Guide
Assembly Lot Code
Silicon Revision
RoHS Compliance Designator
Date Code
Field Description
RoHS Compliant Designation
,
3
1
,
1
4
CKIN
.
Table 21
Table 10
5
CKIN
and
Rev. PrC | Page 23 of 46 | August 2010
specification is 24 MHz.
Figure 8
to
for power-up reset timing.
11 × t
Min
VCO
12
10
10
1.8 V Nominal
, f
CKIN
CCLK
V
DDEXT
, and f
TBD
SCLK
Max
50
settings discussed in
11 × t
2.5/3.3 V Nominal
Min
12
10
10
CKIN
Table 10 on Page 19
V
DDEXT
ADSP-BF592
10
Max
50
through
Unit
MHz
ns
ns
ns
ns