ADSP-BF592KCPZ Analog Devices Inc, ADSP-BF592KCPZ Datasheet - Page 35

• Manufacturer Part Number: ADSP-BF592KCPZ
• Description: 58T4522
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF592KCPZ

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Rohs Compliant: YES
• Frequency: 400MHz
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 32
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Core Supply Voltage: 1.4V
• Lead Free Status / RoHS Status: Compliant

Preliminary Technical Data
Timer Cycle Timing
Table 31
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
Table 31. Timer Cycle Timing
1
2
Timer Clock Timing
Table 32
Table 32. Timer Clock Timing
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PG0 or PPI_CLK signals in PWM output mode.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
Parameter
Switching Characteristic
t
WL
WH
TIS
TIH
HTO
TOD
TODP
and
and
SCLK
Figure 21
Figure 22
Timer Pulse Width Input Low
(Measured In SCLK Cycles)
Timer Pulse Width Input High
(Measured In SCLK Cycles)
Timer Input Setup Time Before CLKOUT Low
Timer Input Hold Time After CLKOUT Low
Timer Pulse Width Output
(Measured In SCLK Cycles)
Timer Output Update Delay After CLKOUT High
Timer Output Update Delay After PPI_CLK High
/2) MHz.
TMRx OUTPUT
TMRx OUTPUT
TMRx INPUT
CLKOUT
PPI_CLK
describe timer expired operations. The
describe timer clock timing.
1
1
Rev. PrC | Page 35 of 46 | August 2010
t
TIS
2
Figure 22. Timer Clock Timing
Figure 21. Timer Cycle Timing
2
t
WH
,t
WL
t
TIH
t
TOD
Min
TBD
TBD
TBD
TBD
TBD
Min
1.8V Nominal
V
DDEXT
V
DDEXT
= 1.8 V
t
HTO
t
Max
Max
TODP
TBD
TBD
TBD
t
t
t
SCLK
SCLK
SCLK
2.5/3.3V Nominal
Min
Min
V
–2
8
DDEXT
– 1.5
+ 1
+ 1
V
= 2.5/3.3 V
DDEXT
ADSP-BF592
(2
32
– 1) × t
12.64
Max
Max
8.1
SCLK
Unit
ns
ns
ns
ns
ns
ns
Unit
ns