FPD85308VJD National Semiconductor, FPD85308VJD Datasheet
FPD85308VJD
Specifications of FPD85308VJD
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FPD85308VJD Summary of contents
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... EEPROM to read the display identification data or program initialization values used by the FPD85308. System Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2001 National Semiconductor Corporation Features n FPD-Link System Interface utilizes Low Voltage Differential Signaling (LVDS). n Supports Graphics Controllers with Spread Spectrum ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Storage Temperature Range (T ) STG Lead Temperature ( (Soldering 10 sec.) ESD Rating 120 pF 1500 ) ZAP ZAP ...
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Device Specifications T Note 3: Measurements DIFF Note 4: RCCS measured between earliest and latest LVDS edges ± Note 5: * RxIN3 pair (RxIN_3 ) is option for 24-bit color depth FIGURE 3. FPD85308 (Receiver) Channel-to-Channel ...
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Device Specifications R/G/B[5] are MSBs and R/G/B[0] are LSBs R/G/B[7] are MSBs and R/G/B[0] are LSBs Symbol Parameter SPsetup E/OSP from E/OCLK SPhold E/OSP from E/OCLK RGBsetup ER/EG/EB/OR/OG/OB from E/OCLK RGBhold ER/EG/EB/OR/OG/OB from E/OCLK CLKpw E/OCLK pulsewidth CLKperiod E/OCLK period ...
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Device Specifications T = 0˚C to 70˚ 3.3V (unless otherwise specified) (Continued FIGURE 6. Column Driver Bus AC Timing FIGURE 7. Vertical Backporch Definition (Video Data from Host) FIGURE 8. Horizontal Backporch Definition (Video Data from ...
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Device Specifications Internal Pixel Count final value = pixels per line/2 Maximum Internal Pixel Count = 1024 (32.5 MHz clocks) Internal Pixel Count is used to generate the horizontal_component for GPO generation See Figure 11 ** Without Blanking control (GPO8), ...
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Device Specifications T = 0˚C to 70˚ 3.3V (unless otherwise specified) (Continued GPO Generation GPO Combination Select FIGURE 11. GPO Control Generation 7 DS101356-20 DS101356-21 www.national.com ...
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Device Specifications Vertical Backporch = 35 Lines/Frame = 825 Pixels/Line = 1200 Horizontal Backporch = 100 Displayed pixels/line = 1024 (Valid data during ENAB High time) Displayed lines/frames = 768 Frequency = 65 MHz (or less) Block Diagram www.national.com T ...
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Functional Description FPD-LINK Receiver The LVDS based FPD-Link Receiver receives inputs video data and control timing. Four LVDS channels plus clock provide 24-bit color. Three LVDS channels can be used for 18-bit color. The video data is regenerated to a ...
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Functional Description White Data The White Data function generates all “1” data beginning at line 769 and continuing until the beginning of the next frame. This function is controlled via D6 Register Bit 7. Timing Control The Timing Control function ...
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Functional Description INPUT FORMAT FIXED VERTICAL, FIXED HORIZONTAL determined by the INPUT CONTROL REGISTER bits [1:0] FIXED VERTICAL, FIXED HORIZONTAL (FIX VERTICAL = 1, FIX HORIZONTAL = 1) FIXED VERTICAL, FIXED HORIZONTAL ENABLE (FIXED VERTICAL = 1, FIXED HORIZONTAL = ...
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Functional Description PROGRAMMABLE REGISTERS At power-up, data is read from an external EEPROM. If anything other than 00H is read back on the first EEPROM access (indicating EEPROM not present), the internal de- TABLE 2. FPD85308 Programmable Register Definition Control ...
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Functional Description TABLE 2. FPD85308 Programmable Register Definition (Continued) Control EEPROM The control registers provide mode setting information to the input and output interfaces. Registers Address Output DB [0] Enable/Polarity [1] Control [2] [3] [4] [5] [7:6] Output Drive D4 ...
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Functional Description TABLE 2. FPD85308 Programmable Register Definition (Continued) Control EEPROM The control registers provide mode setting information to the input and output interfaces. Registers Address Vertical DA HSYNCS from VSYNC falling edge until start of video ...
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Functional Description TABLE 2. FPD85308 Programmable Register Definition (Continued) Control EEPROM The control registers provide mode setting information to the input and output interfaces. Registers Address Control Register [0]. Output polarity - defines active high or active low output (5 ...
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Functional Description Address 94,93 gpo [6]_pstart_reg (10) 96,95 gpo [6]_pcount_reg (11) 98,97 gpo [6]_lstart_reg (11) 9A,99 gpo [6]_lcount_reg (11) 9B gpo [6]_cont_reg (5) 9D,9C gpo [5]_pstart_reg (10) 9F,9E gpo [5]_pcount_reg (11) A1,A0 gpo [5]_lstart_reg (11) A3,A2 gpo [5]_lcount_reg (11) A4 ...
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Functional Description Address D8,D7 hbp_reg (11) DA,D9 vbp_reg (11) DB output_enable/polarity_control (8) FF–DC not used/not loaded Note 7: Programmable CD Size “n” (up to 128) Note 8: One or both clocks can be used Note 9: Unused clocks can be ...
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Functional Description Note 11: Programmable CD Size “n” (up to 128) Note 12: Data skewed to reduce simultaneous switching FIGURE 13. Dual Bus Single Port Column Driver Interface www.national.com (Continued) (Skewed outputs) 18 DS101356-5 ...
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Functional Description Note 13: One or both clocks can be used Note 14: Unused clock can be turned off FIGURE 14. Dual Bus Dual Port Column Driver Interface (Continued) (Non-skewed outputs) 19 DS101356-6 www.national.com ...
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Functional Description Note 15: Data skewed to reduce simultaneous switching FIGURE 15. Dual Bus Dual Port Column Driver Interface www.national.com (Continued) (Skewed outputs) 20 DS101356-7 ...
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Functional Description Note 16: ECLK/ERGB not used — These outputs can be disabled by setting bits 2 and 5 to “0” in the Output Enable/Polarity Control register. Note 17: Start pulse offset * (D3 [1:0]) is defined as below only ...
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Functional Description Note 21: RSTZ transition Low-to-High occurs at the completion of the RPLLS delay or later as shown above. Note 22: All outputs* forced low in default timing of FPD85308 during power-up delay time. Note 23: All outputs ** ...
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... Functional Description Connection Diagram (Continued) DS101356-11 FIGURE 19. Delay Circuit for Stable RSTZ Order Number FPD85308VJD See NS Package Number VJD100A 23 DS101356-2 www.national.com ...
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Pin Description Pin No: Pin Name Pin Count SYSTEM INTERFACE ± 2 RXIN_0 ± 2 RXIN_1 ± 2 RXIN_2 ± 2 RXIN_3 ± 2 RXCLK 1 RSTZ COLUMN DRIVER INTERFACE 1 ECLK 1 ESP 6 ER0..ER5 6 EG0..EG5 6 EB0..EB5 ...
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Pin Description (Continued) • P — Power • G — Ground STI — Schmitt Trigger Input 25 www.national.com ...
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APPENDIX A: GPO Programming Examples The GPO control generation is based on the internal line count and pixel count shown in Figure 9 and Figure 10 . Two programmable registers (Vertical Start and Vertical Duration) control the vertical component of ...
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APPENDIX A: GPO Programming Examples GPO Programming Example #1: Generate a control signal which transitions high at the end of each line, has a pulsewidth of 3 µs, and remains low during the vertical blanking period. This control is used ...
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APPENDIX A: GPO Programming Examples (Continued) GPO Programming Example #2: Generate a control signal which transitions low 20 output clocks after the beginning of each output line, has a pulse- width (low µs, and goes high during horizontal ...
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APPENDIX A: GPO Programming Examples (Continued) GPO Programming Example #3: Generate a control signal which toggles during horizontal blanking and alternates polarity each frame. This control signal is used as the reversal signal. Control is active beginning at line 1 ...
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... APPENDIX B: National Semiconductor FPD85308 REQUEST FORM OF MASK VERSION Company Name:_________________________________Dept:______________________ Tel: _____________________ Model Name (Application): ______________________________________________ Register Values: TABLE 5. Register Values for GPO[0:8]’s Programming Pin Name Address 81 82 GPO8 Value Address 8A 8B GPO7 Value Address 93 94 GPO6 Value Address 9C 9D ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...