LMK04031BISQ National Semiconductor, LMK04031BISQ Datasheet - Page 21

• Manufacturer Part Number: LMK04031BISQ
• Manufacturer: National Semiconductor

Specifications of LMK04031BISQ

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Note 18: For LMK040x0, f
VCO_DIV = 3, N2 = 5, R2 = 1, F
Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
Note 19: For LMK040x1, f
VCO_DIV = 3, N2 = 5, R2 = 1, F
Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
Note 20: For LMK040x2, f
VCO_DIV = 2, N2 = 8, R2 = 1, F
Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
Note 21: For LMK040x3, f
VCO_DIV = 2, N2 = 10, R2 = 1, F
100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
Note 22: For LMK040x0, f
VCO_DIV = 5, N2 = 5, R2 = 2, F
Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = Bypass. CLKout_DLY = OFF.
Note 23: For LMK040x1, f
VCO_DIV = 3, N2 = 5, R2 = 1, F
Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = 2. CLKout_DLY = OFF.
Note 24: For LMK040x2, f
VCO_DIV = 7, N2 = 5, R2 = 2, F
Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = Bypass. CLKout_DLY = OFF.
Note 25: For LMK040x3, f
VCO_DIV = 2, N2 = 10, R2 = 1, F
100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = 4. CLKout_DLY = OFF.
Note 26: For LMK040x0, F
of PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, F
CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100
kHz: -147 dBc/Hz.
Note 27: For LMK040x1, F
of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, F
CLKDIST parameters: CLKoutX_DIV = 2, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz:
-147 dBc/Hz.
Note 28: For LMK040x2, F
of PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, F
CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100
kHz: -147 dBc/Hz.
Note 29: For LMK040x3, F
of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, F
CLKDIST parameters: CLKoutX_DIV = 4, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz:
-147 dBc/Hz.
Note 30: Max jitter specification applies to CH3 (LVPECL) output and guaranteed by test in production.
Note 31: For LMK040x0, F
(model: VXB1-1127-12M288000) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 5, N2 = 10, EN_PLL2_REF2X = 1, F
24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150 pF, C4 = 60 pF, LBW = 109 kHz, PM = 43°, CLKoutX_DIV
= 2, CLKout_DLY = OFF.
Note 32: For LMK040x1, F
(model: ECX-6465) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 3, N2 = 20, EN_PLL2_REF2X = 1, F
ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150 pF, C4 = 60 pF, LBW = 103 kHz, PM = 44°, CLKoutX_DIV = 2, CLKout_DLY
= OFF.
Note 33: For LMK040x2, F
(model: VXB1-1127-12M288000) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 7, N2 = 10, EN_PLL2_REF2X = 1, F
24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150 pF, C4 = 60 pF, LBW = 120 kHz, PM = 40°, CLKoutX_DIV
= 2, CLKout_DLY = OFF.
Note 34: For LMK040x3, F
(model: ECX-6465) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 4, N2 = 20, EN_PLL2_REF2X = 1, F
ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150 pF, C4 = 60 pF, LBW = 91 kHz, PM = 47°, CLKoutX_DIV = 2, CLKout_DLY
= OFF.
Note 35: For Clock output frequencies > 1 GHz, the maximum allowable clock delay is limited to ½ of a period, or, 0.5/F
Note 36: Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for delay mode.
Note 37: LVPECL/2VPECL is programmable for all NSIDs.
Note 38: Guaranteed by characterization.
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
= 1200 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
= 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
= 1600 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
= 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
= 1250 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
= 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
= 1750 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
= 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
= 1250 MHz. PLL1 parameters: F
= 1500 MHz. PLL1 parameters: F
= 1750 MHz. PLL1 parameters: F
= 2000 MHz. PLL1 parameters: F
= 1228.8 MHz. PLL1 parameters: F
= 1474.56 MHz. PLL1 parameters: F
= 1720.32 MHz. PLL1 parameters: F
= 1966.08 MHz. PLL1 parameters: F
DET
DET
DET
DET
DET
DET
DET
DET
= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 268 kHz, PM = 75°. Wenzel XO phase noise: 100
= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 268 kHz, PM = 75°. Wenzel XO phase noise: 100
= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 252 kHz, PM = 76°. Wenzel XO phase noise: 100
= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 268 kHz, PM = 75°. Wenzel XO phase noise: 100
= 50 MHz, ICP2 = 3.2 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 251 kHz, PM = 76°. Wenzel XO phase noise: 100
= 50 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 354 kHz, PM = 73°. Wenzel XO phase noise: 100
= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 434 kHz, PM = 69°. Wenzel XO phase noise:
= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 434 kHz, PM = 69°. Wenzel XO phase noise:
DET
DET
DET
DET
= 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, LBW = 254 kHz, PM = 81°.
= 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, LBW = 271 kHz, PM = 80°.
= 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, LBW = 360 kHz, PM = 79°.
DET
DET
DET
DET
= 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, LBW = 445 kHz, PM = 76°.
DET
= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input
= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input
= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input
= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input
DET
DET
DET
= 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz Vectron crystal
= 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz Ecliptek crystal
= 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz Vectron crystal
= 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz Ecliptek crystal
21
CLKoutX
.
DET
DET
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= 24.576 MHz,
= 24.576 MHz,
DET
DET
=
=