LFE3-95EA-6FN484I Lattice, LFE3-95EA-6FN484I Datasheet - Page 32

• Manufacturer Part Number: LFE3-95EA-6FN484I
• Description: IC FPGA 92KLUTS 295I/O 484FPBGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-6FN484I

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 4526080
• Number Of I /o: 295
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1096

Lattice Semiconductor
Figure 2-31. MULTADDSUBSUM Slice 1
Advanced sysDSP Slice Features
Cascading
The LatticeECP3 sysDSP slice has been enhanced to allow cascading. Adder trees are implemented fully in sys-
DSP slices, improving the performance. Cascading of slices uses the signals CIN, COUT and C Mux of the slice.
Addition
The LatticeECP3 sysDSP slice allows for the bypassing of multipliers and cascading of adder logic. High perfor-
mance adder functions are implemented without the use of LUTs. The maximum width adders that can be imple-
mented are 54-bit.
Rounding
The rounding operation is implemented in the ALU and is done by adding a constant followed by a truncation oper-
ation. The rounding methods supported are:
• Rounding to zero (RTZ)
• Rounding to infinity (RTI)
• Dynamic rounding
• Random rounding
• Convergent rounding
DSP Slice
Previous
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
Rounding
SRIB
SRIA
C_ALU
A_ALU
CIN
0
IR
C
IR
AA
MULTA
PR
OR
AMUX
A_ALU
IR
From FPGA Core
AB
To FPGA Core
0
R = Logic (B, C)
R= A ± B ± C
2-29
OR
PR
IR
OPCODE
FR
0
=
=
B_ALU
BMUX
IR
ALU
BA
MULTB
OR
PR
LatticeECP3 Family Data Sheet
IR
BB
IR
COUT
SROB
SROA
DSP Slice
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Architecture