LC4064ZE-5MN64C Lattice, LC4064ZE-5MN64C Datasheet - Page 4

• Manufacturer Part Number: LC4064ZE-5MN64C
• Description: IC PLD 64MC 48I/O 5.8NS 64CSBGA
• Manufacturer: Lattice
• Series: ispMACH®r

Specifications of LC4064ZE-5MN64C

• Programmable Type: CPLD
• Number Of Macrocells: 64
• Voltage - Input: 1.7 V ~ 1.9 V
• Speed: 5.8ns
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1017

Lattice Semiconductor
Figure 3. AND Array
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the ispMACH 4000ZE family is 4+1 (total 5) product
terms. The software automatically considers the availability and distribution of product term clusters as it fits the
functions within a GLB. The logic allocator is designed to provide two speed paths: 20-PT Speed Locking path and
an up to 80-PT path. The availability of these two paths lets designers trade timing variability for increased perfor-
mance.
The enhanced Logic Allocator of the ispMACH 4000ZE family consists of the following blocks:
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
Figure 4. Macrocell Slice
• Product Term Allocator
• Cluster Allocator
• Wide Steering Logic
Individual Product
Term Allocator
Cluster
In[34]
In[35]
In[0]
n
Note:
Indicates programmable fuse.
n+1
to
n-1
to
n-2
to
Allocator
Cluster
4
5-PT
from
n+2
from
n-1
from
from
n+1
n-4
From
PT0
PT1
PT2
PT3
PT4
PT75
PT76
PT77
PT78
PT79
n-4
ispMACH 4000ZE Family Data Sheet
PT80
PT81
PT82
Cluster 0
Cluster 15
Shared PT Clock
Shared PT Initialization
Shared PTOE/BIE
Steering Logic
SuperWIDE™
1-80
PTs
To n+4
To XOR (MC)