ICS95V850AG IDT, Integrated Device Technology Inc, ICS95V850AG Datasheet
ICS95V850AG
Specifications of ICS95V850AG
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ICS95V850AG Summary of contents
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Integrated Circuit Systems, Inc. DDR Phase Lock Loop Clock Driver (60MHz - 210MHz) Recommended Application: DDR Clock Driver Product Description/Features: • Low skew, low jitter PLL clock driver • Feedback pins for input to output synchronization • Spread Spectrum tolerant ...
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ICS95V850 Pin Descriptions ...
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Absolute Maximum Ratings Supply Voltage: (VDD & AVDD -0.5V to 3.6V Input clamp current: I (VI < > VDD ...
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ICS95V850 Recommended Operating Condition (see note1 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) A PARAMETER SYMBOL Supply Voltage VDD Low level input voltage V IL High ...
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Switching Characteristics (see note 3) PARAMETER Low-to high level propagation delay time High-to low level propagation delay time Period jitter Half-period jitter Input clock slew rate Output clock slew rate 1 Cycle to Cycle Jitter Phase error Output to Output ...
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ICS95V850 V DD/2 ICS95V850 -V DD/2 NOTE: V (TT) = GND Y , FB_OUTC FB_OUTT X 0458G—11/21/08 Parameter Measurement Information (CLKC) V (CLKC) ICS95V850 GND Figure 1. IBIS Model Output Load ...
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CLK_INC CLK_INT FB_INC FB_INT FB_OUTC FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 0458G—11/21/08 Parameter Measurement Information ...
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ICS95V850 Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 0458G—11/21/08 Parameter Measurement Information t (hper_n+1) t (hper_n (jit_Hper) (jit_Hper_n) 2xf O Figure 7. Half-Period Jitter 80% Rise ...
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Recommended Layout for the ICS95V850 General Layout Precautions: Use copper flooded ground on the top signal layer under the clock buffer The area under U1 on the right is an example. Flood over the ground vias. 1) Use power vias ...
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ICS95V850 INDEX INDEX AREA AREA aaa 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information 95V850yLFGT Example: XXXX y G (LF ...