ICS95V850AG IDT, Integrated Device Technology Inc, ICS95V850AG Datasheet - Page 5

• Manufacturer Part Number: ICS95V850AG
• Description: IC CLK DVR PLL 1:10 48TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Driver, PLLr

Specifications of ICS95V850AG

• Input: Clock
• Output: SSTL-2
• Frequency - Max: 210MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 210MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 95V850AG

Notes:
1.
2.
3.
4. Static phase offset shifted by design.
0458G—11/21/08
Low-to high level
propagation delay time
High-to low level propagation
delay time
Period jitter
Half-period jitter
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter
Phase error
Output to Output Skew
Switching Characteristics (see note 3)
Refers to transition on noninverting output in PLL bypass mode.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
the cycle (t
Switching characteristics guaranteed for application frequency range.
PARAMETER
c
) decreases as the frequency goes up.
1
t
SYMBOL
t(jit_hper)
(phase error)
T
T
cyc
T
t
t
t
jit (per)
PLH
t
PLL
sl(o)
skew
sl(i)
-T
1
1
cyc
4
CLK_IN to any output
CLK_IN to any output
100MHz to 200MHz
100MHz to 200MHz
100MHz to 200MHz
CONDITION
5
wH
/t
c
, where
MIN
-30
-75
-50
1
1
TYP
5.5
5.5
0
ICS95V850
MAX
2.5
30
30
60
50
60
4
UNITS
V/ns
V/ns
ns
ns
ps
ps
ps
ps
ps