ICS932S208DG IDT, Integrated Device Technology Inc, ICS932S208DG Datasheet - Page 18

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ICS932S208DG

Manufacturer Part Number
ICS932S208DG
Description
IC TIMING HUB CTRL PROGR 56TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Timing Control Hubr
Datasheet

Specifications of ICS932S208DG

Input
Crystal
Output
Clock
Frequency - Max
200MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
932S208DG

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Differential Clock Tristate
IDT
To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or
tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or tristated during
PCI_Stop# and PwrDwn# mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the
corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_Stop",
"SRC_Stop" and "PwrDwn" register bit settings.
Notes:
1. Each output has four corresponding control register bits, OE, PwrDwn, CPU_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address
Notes:
1. SRC output has four corresponding control register bits, OE, PwrDwn, SRC_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address
C
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ICS932S208
Programmable Timing Control Hub
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2
0743G—01/26/10

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