MC100EP195BMNR4G ON Semiconductor, MC100EP195BMNR4G Datasheet - Page 11

• Manufacturer Part Number: MC100EP195BMNR4G
• Description: IC PROGRAM DELAY 3.3V ECL 32-QFN
• Manufacturer: ON Semiconductor
• Series: 100EPr
• Type: Programmable Delay Chipr

Specifications of MC100EP195BMNR4G

• Input: ECL, LVCMOS, LVTTL
• Output: ECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TFQFN Exposed Pad
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC100EP195BMNR4GOS; MC100EP195BMNR4GOS; MC100EP195BMNR4GOSTR

Cascading Multiple EP195Bs
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP195Bs without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E195B.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range: however, this
increase is at the expense of a longer minimum delay.
two EP195Bs. As can be seen, this scheme can easily be
Table 10. AC CHARACTERISTICS
Symbol
Symbol
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V
15. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
16. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
17. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
18. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater
19. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output re-
20. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
21. Deviation from a linear delay (actual Min to Max) in the 1024 programmable steps.
V
t
t
r
f
To increase the programmable range of the EP195B,
Figure 5 illustrates the interconnect scheme for cascading
PP
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
than ±75 mV to that IN/IN transition.
sponse greater than ±75 mV to that IN/IN transition.
the specified IN to Q propagation delay and transition times.
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
Input Voltage Swing
(Differential Configuration)
Output Rise/Fall Time @ 50 MHz
Characteristic
Characteristic
20−80% (CASCADE)
20−80% (Q)
V
CC
IN
IN
Q
Q
= 0 V; V
Figure 4. AC Reference Measurement
t
PLH
EE
Min
150
110
85
= −3.0 V to −3.6 V or V
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−40°C
Typ
800
115
160
11
expanded for larger EP195B chains. The D10 input of the
EP195B is the CASCADE control pin. With the
interconnect scheme of Figure 5 when D10 is asserted, it
signals the need for a larger programmable range than is
achievable with a single device and switches output pin
CASCADE HIGH and pin CASCADE LOW. The A11
address can be added to generate a cascade output for the
next EP195B. For a 2−device configuration, A11 is not
required.
1200
Max
140
210
CC
t
Min
150
100
120
PHL
V
V
= 3.0 V to 3.6 V; V
INPP
OUTPP
25°C
= V
Typ
800
120
175
= V
CC
IH
(D) − V
OH
− 2.0 V.
1200
(Q) − V
Max
140
230
EE
IL
(D)
= 0 V (Note 14)
OL
Min
150
100
120
(Q)
85°C
Typ
800
130
190
1200
Max
165
250
Unit
Unit
mV
ps