AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet - Page 2

• Manufacturer Part Number: AD9511BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9511BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9511/PCB - BOARD EVAL CLOCK DISTR 48LFCSPAD9511-VCO/PCB - BOARD EVAL CLOCK DISTR 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9511
TABLE OF CONTENTS
Specifications..................................................................................... 4
Timing Diagrams............................................................................ 17
Absolute Maximum Ratings.......................................................... 18
Pin Configuration and Function Descriptions........................... 19
Terminology .................................................................................... 21
Typical Performance Characteristics ........................................... 22
Typical Modes of Operation.......................................................... 26
Functional Description .................................................................. 29
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 5
Clock Outputs ............................................................................... 6
Timing Characteristics ................................................................ 7
Clock Output Phase Noise .......................................................... 9
Clock Output Additive Time Jitter........................................... 12
PLL and Distribution Phase Noise and Spurious................... 14
Serial Control Port ..................................................................... 15
FUNCTION Pin ......................................................................... 15
STATUS Pin ................................................................................ 16
Power............................................................................................ 16
Thermal Characteristics ............................................................ 18
ESD Caution................................................................................ 18
PLL with External VCXO/VCO Followed by Clock
Distribution................................................................................. 26
Clock Distribution Only............................................................ 26
PLL with External VCO and Band-Pass Filter Followed by
Clock Distribution...................................................................... 27
Overall.......................................................................................... 29
PLL Section ................................................................................. 29
PLL Reference Input—REFIN .............................................. 29
VCO/VCXO Clock Input—CLK2........................................ 29
PLL Reference Divider—R .................................................... 29
VCO/VCXO Feedback Divider—N (P, A, B) ..................... 29
Rev. A | Page 2 of 60
FUNCTION Pin ......................................................................... 32
Distribution Section................................................................... 33
CLK1 and CLK2 Clock Inputs.................................................. 33
Dividers........................................................................................ 33
Delay Block ................................................................................. 38
Outputs ........................................................................................ 38
Power-Down Modes .................................................................. 39
Reset Modes ................................................................................ 40
A and B Counters................................................................... 30
Determining Values for P, A, B, and R ................................ 30
Phase Frequency Detector (PFD) and Charge Pump ....... 31
Antibacklash Pulse................................................................. 31
STATUS Pin ............................................................................ 31
PLL Digital Lock Detect........................................................ 31
PLL Analog Lock Detect ....................................................... 32
Loss of Reference.................................................................... 32
RESETB: 58h<6:5> = 00b (Default)..................................... 32
SYNCB: 58h<6:5> = 01b ....................................................... 32
PDB: 58h<6:5> = 11b ............................................................ 33
Setting the Divide Ratio ........................................................ 33
Setting the Duty Cycle........................................................... 33
Divider Phase Offset.............................................................. 37
Calculating the Delay ............................................................ 38
Chip Power-Down or Sleep Mode—PDB........................... 39
PLL Power-Down................................................................... 39
Distribution Power-Down .................................................... 39
Individual Clock Output Power-Down............................... 39
Individual Circuit Block Power-Down................................ 39
Power-On Reset—Start-Up Conditions when VS
is Applied................................................................................. 40
Asynchronous Reset via the FUNCTION Pin ................... 40
Soft Reset via the Serial Port................................................. 40