IC CLOCK DISTRIB CHIP 1:4 16SOIC

MC100EL15DG

Manufacturer Part NumberMC100EL15DG
DescriptionIC CLOCK DISTRIB CHIP 1:4 16SOIC
ManufacturerON Semiconductor
Series100EL
TypeFanout Buffer (Distribution), Multiplexer
MC100EL15DG datasheet
 


Specifications of MC100EL15DG

Number Of Circuits1Ratio - Input:output2:4
Differential - Input:outputYes/YesInputECL, PECL
OutputECL, PECLFrequency - Max1.25GHz
Voltage - Supply4.2 V ~ 5.7 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case16-SOIC (3.9mm Width)
Frequency-max1.25GHzLead Free Status / RoHS StatusLead free / RoHS Compliant
Other namesMC100EL15DGOS  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
Page 1/8

Download datasheet (148Kb)Embed
Next
MC10EL15, MC100EL15
5V ECL 1:4 Clock
Distribution Chip
The MC10EL/100EL15 is a low skew 1:4 clock distribution chip
designed explicitly for low skew clock distribution applications. The
V
pin, an internally generated voltage supply, is available to this device
BB
only. For single-ended input conditions, the unused differential input is
connected to V
as a switching reference voltage. V
BB
AC coupled inputs. When used, decouple V
capacitor and limit current sourcing or sinking to 0.5 mA. When not used,
V
should be left open.
BB
The EL15 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high
speed system clock. When LOW (or left open and pulled LOW by the
input pulldown resistor) the SEL pin will select the differential clock
input.
The common enable (EN) is synchronous so that the outputs will
only be enabled/disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock,
therefore all associated specification limits are referenced to the
negative edge of the clock input.
The 100 series contains temperature compensation.
Features
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
PECL Mode Operating Range: V
CC
with V
= 0 V
EE
NECL Mode Operating Range: V
CC
with V
= −4.2 V to −5.7 V
EE
Internal Input Pulldown Resistors on CLKs, SCLK, SEL, and EN.
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 5
may also rebias
BB
and V
via a 0.01 mF
BB
CC
= 4.2 V to 5.7 V
*For additional marking information, refer to
= 0 V
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
1
http://onsemi.com
16
1
SO−16
D SUFFIX
CASE 751B
MARKING DIAGRAMS*
10EL15G
100EL15G
AWLYWW
AWLYWW
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
Application Note AND8002/D.
ORDERING INFORMATION
Publication Order Number:
MC10EL15/D

MC100EL15DG Summary of contents

  • Page 1

    ... Internal Input Pulldown Resistors on CLKs, SCLK, SEL, and EN. • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 August, 2005 − Rev. 5 ...

  • Page 2

    V EN SCLK CLK Figure 1. Logic Diagram and Pinout Assignment Table 1. PIN DESCRIPTION PIN FUNCTION CLK, CLK ECL Diff Clock Inputs SCLK ECL Scan Clock Input EN ECL Sync ...

  • Page 3

    Table 4. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...

  • Page 4

    Table 6. 10EL SERIES NECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...

  • Page 5

    Table 8. 100EL SERIES NECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 13 Output LOW Voltage (Note 13 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...

  • Page 6

    ... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC10EL15D MC10EL15DG MC10EL15DR2 MC10EL15DR2G MC100EL15D MC100EL15DG MC100EL15DR2 MC100EL15DR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ ...

  • Page 7

    Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...

  • Page 8

    ... American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. ...