MC100LVE310FNR2G ON Semiconductor, MC100LVE310FNR2G Datasheet

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MC100LVE310FNR2G

Manufacturer Part Number
MC100LVE310FNR2G
Description
IC BUFFER FANOUT ECL 2:8 28PLCC
Manufacturer
ON Semiconductor
Series
100LVEr
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet

Specifications of MC100LVE310FNR2G

Number Of Circuits
1
Ratio - Input:output
2:8
Differential - Input:output
Yes/Yes
Input
LVECL, LVPECL
Output
LVECL, LVPECL
Frequency - Max
1GHz
Voltage - Supply
3 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-PLCC
Frequency-max
1GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC100LVE310FNR2GOS
MC100LVE310FNR2GOS
MC100LVE310FNR2GOSTR

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MC100LVE310
3.3V ECL 2:8 Differential
Fanout Buffer
Description
fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and
system skew. The LVE310 offers two selectable clock inputs to allow
for redundant or test clocks to be incorporated into the system clock
trees.
both sides of the differential output are terminated into 50 W, even if
only one side is being used. In most applications all eight differential
pairs will be used and therefore terminated. In the case where fewer
than eight pairs are used it is necessary to terminate at least the output
pairs adjacent to the output pair being used in order to maintain
minimum skew. Failure to follow this guideline will result in small
degradations of propagation delay (on the order of 10 - 20 ps) of the
outputs being used, while not catastrophic to most designs this will
result in an increase in skew. Note that the package corners isolate
outputs from one another such that the guideline expressed above
holds only for outputs on the same side of the package.
from a positive V
LVE310 to be used for high performance clock distribution in +3.3 V
systems. Designers can take advantage of the LVE310's performance
to distribute low skew clocks across the backplane or the board. In a
PECL environment series or Thevenin line terminations are typically
used as they require no additional power supplies, if parallel
termination is desired a terminating voltage of V
to be provided. For more information on using PECL, designers
should refer to Application Note AN1406/D.
this device only. For single‐ended input conditions, the unused
differential input is connected to V
V
and V
to 0.5 mA. When not used, V
Features
*For additional information on our Pb-Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2007
October, 2007 - Rev. 5
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
BB
The MC100LVE310 is a low voltage, low skew 2:8 differential ECL
To ensure that the tight skew specification is met it is necessary that
The MC100LVE310, as with most ECL devices, can be operated
The V
200 ps Part-to-Part Skew
50 ps Output-to-Output Skew
PECL Mode Operating Range:
NECL Mode Operating Range:
V
V
may also rebias AC coupled inputs. When used, decouple V
CC
CC
CC
BB
= 3.0 V to 3.8 V with V
= 0 V with V
via a 0.01 mF capacitor and limit current sourcing or sinking
pin, an internally generated voltage supply, is available to
CC
EE
supply in LVPECL mode. This allows the
= -3.0 V to -3.8 V
BB
should be left open.
EE
BB
= 0 V
as a switching reference voltage.
CC
- 2.0 V will need
1
BB
Q Output will Default LOW with All Inputs Open or
at V
The 100 Series Contains Temperature Compensation
Pb-Free Packages are Available*
EE
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
A
WL
YY
WW
G
MARKING DIAGRAM*
http://onsemi.com
MC100LVE310G
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
FN SUFFIX
CASE 776
PLCC-28
Publication Order Number:
1
MC100LVE310/D

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MC100LVE310FNR2G Summary of contents

Page 1

... NECL Mode Operating Range with *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2007 October, 2007 - Rev 2.0 V will need switching reference voltage. ...

Page 2

CCO CLK_SEL 28 CLKa Pinout: 28-Lead PLCC (Top View) CLKa CLKb CLKb NC ...

Page 3

Table 4. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...

Page 4

Table 6. LVNECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single-Ended Input LOW Voltage (Single-Ended Output ...

Page 5

... Application Note AND8020/D - Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVE310FN MC100LVE310FNG MC100LVE310FNR2 MC100LVE310FNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D ...

Page 6

0.010 (0.250 NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT ...

Page 7

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT:  Literature Distribution Center for ON Semiconductor  P.O. Box 5163, Denver, Colorado 80217 USA  Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada  Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada   ...

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