ICS853310AVLF IDT, Integrated Device Technology Inc, ICS853310AVLF Datasheet

IC FANOUT BUFFER LVPECL 28-PLCC

ICS853310AVLF

Manufacturer Part Number
ICS853310AVLF
Description
IC FANOUT BUFFER LVPECL 28-PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet

Specifications of ICS853310AVLF

Number Of Circuits
1
Ratio - Input:output
2:8
Differential - Input:output
Yes/Yes
Input
CML, LVDS, LVPECL, SSTL
Output
ECL, LVPECL
Frequency - Max
2GHz
Voltage - Supply
3 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-PLCC
Frequency-max
2GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1172
800-1172-5
800-1172
853310AVLF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS853310AVLF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ICS853310AVLFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
B
G
pairs can accept LVPECL, LVDS, CML and SSTL differential
input levels. The ICS853310 is characterized to operate from
a 3.3V power supply. Guaranteed output and part-to-part
skew characteristics make the ICS853310 ideal for those
clock distribution applications demanding well defined per-
formance and repeatability.
853310AV
HiPerClockS™
IC S
CLK_SEL
LOCK
ENERAL
nPCLK0
nPCLK1
PCLK0
PCLK1
V
BB
D
The ICS853310 is a low skew, high perfor-
mance 1-to-8 Differential-to-3.3V LVPECL/ECL
Fa n o u t B u f fe r a n d a m e m b e r o f t h e
HiPerClockS ™ family of High Performance
Clock Solutions from ICS. The PCLKx, nPCLKx
IAGRAM
Integrated
Circuit
Systems, Inc.
D
ESCRIPTION
0
1
www.icst.com/products/hiperclocks.html
D
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
IFFERENTIAL
1
F
• Eight differential 3.3V LVPECL / ECL outputs
• Two selectable differential LVPECL input pairs
• PCLKx, nPCLKx pairs can accept the following
• Output frequency: >2GHz (typical)
• Translates any single ended input signal to 3.3V
• Output skew: 50ps (maximum)
• Part-to-part skew: 200ps (maximum)
• Propagation delay: 900ps (maximum)
• LVPECL mode operating voltage supply range:
• ECL mode operating voltage supply range:
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
P
-
TO
differential input levels: LVPECL, LVDS, CML, SSTL
LVPECL levels with resistor bias on nPCLKx input
V
V
packages
EATURES
IN
CC
CC
-3.3V LVPECL/ECL F
= 3V to 3.8V, V
= 0V, V
A
CLK_SEL
nPCLK0
PCLK0
PCLK1
SSIGNMENT
11.6mm x 11.4mm x 4.1mm package body
V
V
V
CC
EE
BB
EE
= -3V to -3.8V
26
27
28
1
2
3
4
25
5
EE
= 0V
24
6
28-Lead PLCC
ICS853310
V Package
23
Top View
7
22
8
L
21
OW
9
ICS853310
10
20 19
ANOUT
S
REV. A OCTOBER 27, 2008
11
KEW
18
17
16
15
14
13
12
, 1-
B
Q3
nQ3
Q4
V
nQ4
Q5
nQ5
CCO
UFFER
TO
-8

Related parts for ICS853310AVLF

ICS853310AVLF Summary of contents

Page 1

Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS853310 is a low skew, high perfor mance 1-to-8 Differential-to-3.3V LVPECL/ECL HiPerClockS™ ...

Page 2

Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...

Page 3

Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage, V 4.6V (LVPECL mode Negative Supply Voltage, V -4.6V (LVECL mode Inputs, V (LVPECL mode) -0. Inputs, V (LVECL mode) 0.5V ...

Page 4

Integrated Circuit Systems, Inc. T 2C. LVECL ABLE OWER UPPLY ...

Page 5

Integrated Circuit Systems, Inc. P ARAMETER LVPECL V EE -1.3V ± 0. UTPUT OAD EST IRCUIT nQx Qx nQy Qy tsk( UTPUT KEW nPCLK0, nPCLK1 PCLK0, PCLK1 nQ0:nQ7 Q0:Q7 t ...

Page 6

Integrated Circuit Systems, Inc IRING THE IFFERENTIAL NPUT TO Figure 1A shows an example of the differential input that can be wired to accept single ended LVCMOS levels. The reference voltage level V generated from the device ...

Page 7

Integrated Circuit Systems, Inc. LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING and V input requirements. Figures show inter- CMR face examples ...

Page 8

Integrated Circuit Systems, Inc ECOMMENDATIONS FOR NUSED I : NPUTS PCLK/nPCLK I : NPUT For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, ...

Page 9

Integrated Circuit Systems, Inc CHEMATIC XAMPLE Figure 4A shows a schematic example of the ICS853310. In this example, the PCLK0/nPCLK0 input is selected. The decoupling VCC Ohm Ohm LVPECL Driv er R9 ...

Page 10

Integrated Circuit Systems, Inc OWER ROUND AND YPASS APACITOR This section provides a layout guide related to power, ground and placement of bypass capacitors for a high-speed digital IC. This layout guide is a general ...

Page 11

Integrated Circuit Systems, Inc. This section provides information on power dissipation and junction temperature for the ICS853310. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853310 is the sum of the core ...

Page 12

Integrated Circuit Systems, Inc. 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 5. Figure 5. LVPECL Driver Circuit and Termination T o calculate worst case power dissipation into the load, use the following equations ...

Page 13

Integrated Circuit Systems, Inc. θ ABLE VS IR LOW ABLE FOR JA θ θ θ θ θ Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in ...

Page 14

Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MS-018 853310AV D - -3.3V LVPECL/ECL F IFFERENTIAL TO PLCC EAD ACKAGE IMENSIONS J E ...

Page 15

Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...

Page 16

Integrated Circuit Systems, Inc ...

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