MB15F07SLPFV1-BND-6E1 Fujitsu Semiconductor America Inc, MB15F07SLPFV1-BND-6E1 Datasheet - Page 8

• Manufacturer Part Number: MB15F07SLPFV1-BND-6E1
• Description: SYNTHESZR PLL 1.1GHZ DUAL 16SSOP
• Manufacturer: Fujitsu Semiconductor America Inc
• Type: Clock/Frequency Synthesizer (RF/IF), Prescalerr

Specifications of MB15F07SLPFV1-BND-6E1

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 1.1GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Frequency-max: 1.1GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1003-6

8
MB15F07SL
The divide ratio can be calculated using the following equation:
f
f
M :
N
A
f
R
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of PLL 1/PLL 2
sections, programmable reference dividers of PLL 1/PLL 2 sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of serial data is transferred into the shift register. When the LE signal is taken high,
the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table 1. Control Bit
Shift Register Configuration
VCO
VCO
OSC
LSB
FUNCTIONAL DESCRIPTION
C
N
1
1
= {(M
:
:
:
:
:
CN1
CN1, CN2
R1 to R14
T1, T2
CS
X
NOTE: Data input with MSB first.
Programmable Reference Counter
H
H
L
L
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of dual modulus prescaler (64 or 128 for PLL 1/PLL 2)
Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0
Reference oscillation frequency
Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
C
N
2
2
Control bit
N) + A}
3
T
1
4
T
2
: Control bit
: Divide ratio setting bits for the programmable reference counter (3 to 16,383)[Table 2]
: Test purpose bit
: Charge pump currnet select bit
: Dummy bits (Set “0” or “1”)
f
R
5
1
OSC
CN2
H
H
L
L
R
6
2
R (A < N)
R
7
3
The programmable reference counter for the PLL 1
The programmable reference counter for the PLL 2
The programmable counter and the swallow counter for the PLL 1
The programmable counter and the swallow counter for the PLL 2
R
8
4
R
9
5
10 11 12 13 14 15 16 17 18 19 20 21 22 23
R
6
R
7
Data Flow
R
8
R
9
Destination of serial data
A
10
R
127)
11
R
12
R
13
R
14
R
C
S
X
X
[Table 1]
[Table 3]
[Table 9]
X
MSB
X