SI4136-F-GT Silicon Laboratories Inc, SI4136-F-GT Datasheet - Page 16

• Manufacturer Part Number: SI4136-F-GT
• Description: IC WLAN SAT RADIO 24TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4136-F-GT

• Package / Case: 24-TSSOP
• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 2.5GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 2.5GHz
• Operating Frequency: 62.5 MHz to 1000 MHz
• Supply Current: 25.7 mA
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Power Gain Typ: 3.5 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1291-5

Si4136/Si4126
2. Functional Description
The Si4136 is a monolithic integrated circuit that
performs IF and dual-band RF synthesis for many
wireless communications applications. This integrated
circuit (IC), along with a minimum number of external
components, is all that is necessary to implement the
frequency synthesis function in applications like W-LAN
using the IEEE 802.11 standard.
The Si4136 has three complete phase-locked loops
(PLLs), with integrated voltage-controlled oscillators
(VCOs). The low phase noise of the VCOs makes the
Si4136 suitable for use in demanding wireless
communications applications. Also integrated are phase
detectors, loop filters, and reference and output
frequency dividers. The IC is programmed through a
three-wire serial interface.
Two PLLs are provided for RF synthesis. These RF
PLLs are multiplexed so that only one PLL is active at a
given time (as determined by the setting of an internal
register). The active PLL is the last one written. The
center frequency of the VCO in each PLL is set by the
internal bond wire inductance within the package.
Inaccuracies in these inductances are compensated for
by the self-tuning algorithm. The algorithm is run
following power-up or following a change in the
programmed output frequency.
The RF PLLs contain a divide-by-2 circuit before the N-
divider. As a result, the phase detector frequency (f) is
equal to half the desired channel spacing. For example,
for a 200 kHz channel spacing, f would equal 100 kHz.
The IF PLL does not contain the divide-by-2 circuit
before the N-divider. In this case, f is equal to the
desired channel spacing. Each RF VCO is optimized for
a particular frequency range. The RF1 VCO is
optimized to operate from 2.3 GHz to 2.5 GHz, while the
RF2 VCO is optimized to operate between 2.025 GHz
and 2.3 GHz.
One PLL is provided for IF synthesis. The center
frequency of this circuit’s VCO is set by an external
inductance. The PLL can adjust the IF output frequency
by ±5% of the VCO center frequency. Inaccuracies in
the value of the external inductance are compensated
for by the Si4136’s proprietary self-tuning algorithm.
This algorithm is initiated each time the PLL is powered-
up (by either the PWDN pin or by software) and/or each
time a new output frequency is programmed. The IF
VCO can have its center frequency set as low as
526 MHz and as high as 952 MHz. An IF output divider
is provided to divide down the IF output frequencies, if
needed. The divider is programmable, capable of
dividing by 1, 2, 4, or 8.
In order to accommodate designs running at XIN
16
Rev. 1.41
frequencies greater than 25 MHz, the Si4136 includes a
programmable
Register 0, D6) on the XIN input. By enabling this
option, the Si4136 can accept a range of TCXO
frequencies from 25 MHz to 50 MHz. This feature
makes the Si4136 ideal for W-LAN radio designs
operating at an XIN of 44 MHz.
The unique PLL architecture used in the Si4136
produces settling (lock) times that are comparable in
speed to fractional-N architectures without suffering the
high phase noise or spurious modulation effects often
associated with those designs.
2.1. Serial Interface
A timing diagram for the serial interface is shown in
Figure 2 on page 7. Figure 3 on page 7 shows the
format of the serial word.
The Si4136 is programmed serially with 22-bit words
comprised of 18-bit data fields and 4-bit address fields.
When the serial interface is enabled (i.e., when SEN is
low) data and address bits on the SDATA pin are
clocked into an internal shift register on the rising edge
of SCLK. Data in the shift register is then transferred on
the rising edge of SEN into the internal data register
addressed in the address field. The serial interface is
disabled when SEN is high.
Table 11 on page 21 summarizes the data register
functions and addresses. It is not necessary (although it
is permissible) to clock into the internal shift register any
leading bits that are “don’t cares.”
2.2. Setting the IF VCO Center Frequencies
The IF PLL can adjust its output frequency ±5% from
the center frequency as established by the value of an
external inductance connected to the VCO. The RF1
and RF2 PLLs have fixed operating ranges due to the
inductance set by the internal bond wires. Each center
frequency is established by the value of the total
inductance (internal and/or external) connected to the
respective VCO. Manufacturing tolerance of ±10% for
the external inductor is acceptable for the IF VCO. The
Si4136 will compensate for inaccuracies by executing a
self-tuning algorithm following
following
frequency.
Because the total tank inductance is in the low nH
range, the inductance of the package needs to be
considered
inductance. The total inductance (L
the IF VCO is the sum of the external inductance (L
and the package inductance (L
nominal capacitance (C
inductance, and the center frequency is as follows:
a
in
change
divide-by-2
determining
in
NOM
the
) in parallel with the total
PKG
option
the
programmed
). The IF VCO has a
PLL
TOT
correct
) presented to
(XINDIV2
power-up
external
output
EXT
or
in
)