SI4136-F-GT Silicon Laboratories Inc, SI4136-F-GT Datasheet - Page 19

• Manufacturer Part Number: SI4136-F-GT
• Description: IC WLAN SAT RADIO 24TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4136-F-GT

• Package / Case: 24-TSSOP
• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 2.5GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 2.5GHz
• Operating Frequency: 62.5 MHz to 1000 MHz
• Supply Current: 25.7 mA
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Power Gain Typ: 3.5 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1291-5

(Register 0) can be set to 1 to reduce the bias currents
and therefore reduce the power dissipated by the IF
amplifier. For loads less than 500  LPWR should be
set to 0 to maximize the output level.
For IF frequencies greater than 500 MHz, a matching
network is required in order to drive a 50  load. See
Figure 15 below. The value of L
determined by Table 9.
Typical values range between 8 nH and 40 nH.
For frequencies less than 500 MHz, the IF output buffer
can directly drive a 200  resistive load or higher. For
resistive loads greater than 500  (f < 500 MHz) the
LPWR bit can be set to reduce the power consumed by
the IF output buffer. See Figure 16 below.
Frequency
500–600 MHz
600–800 MHz
800–1 GHz
Figure 15. IF Frequencies > 500 MHz
Figure 16. IF Frequencies < 500 MHz
IFO UT
IFO UT
Table 9. L
L
>500 pF
MATCH
MATCH
>500 pF
Values
L
40 nH
27 nH
18 nH
MATCH
>200
MATCH
50


can be
Rev. 1.41
2.7. Reference Frequency Amplifier
The Si4136 provides a reference frequency amplifier. If
the driving signal has CMOS levels, it can be connected
directly to the XIN pin. Otherwise, the reference
frequency signal should be AC coupled to the XIN pin
through a 560 pF capacitor.
2.8. Powerdown Modes
Table 10 summarizes the powerdown functionality. The
Si4136 can be powered down by taking the PWDN pin
low or by setting bits in the Powerdown register
(Register 2). When the PWDN pin is low, the Si4136 will
be powered down regardless of the Powerdown register
settings. When the PWDN pin is high, power
management is under control of the Powerdown register
bits.
The IF and RF sections of the Si4136 circuitry can be
individually powered down by setting the Powerdown
register bits PDIB and PDRB low. The reference
frequency amplifier will also be powered up if either the
PDRB and PDIB bits are high. Also, setting the
AUTOPDB bit to 1 in the Main Configuration register
(Register 0) is equivalent to setting both bits in the
Powerdown register to 1.
The serial interface remains available and can be
written in all power-down modes.
2.9. Auxiliary Output (AUXOUT)
The signal appearing on AUXOUT is selected by setting
the AUXSEL bits in the Main Configuration register
(Register 0).
The LDETB signal can be selected by setting the
AUXSEL bits to 011. This signal can be used to indicate
that the IF or RF PLL is about to lose lock due to
excessive ambient temperature drift and should be re-
tuned.
450
400
350
300
250
200
150
100
50
0
0
Figure 17. Typical IF Output Voltage vs.
LPWR=0
200
Load Resistance at 550 MHz
400
Si4136/Si4126
Load Resistance ()
LPWR=1
600
800
1000
1200
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