ICS84330AV-02LF IDT, Integrated Device Technology Inc, ICS84330AV-02LF Datasheet - Page 11

• Manufacturer Part Number: ICS84330AV-02LF
• Description: IC SYNTHESIZER 700MHZ 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Frequency Synthesizerr

Specifications of ICS84330AV-02LF

• Pll: Yes
• Input: LVCMOS, LVTTL, Crystal
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: No/Yes
• Frequency - Max: 700MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 84330AV-02LF

84330AV-02
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
Place the decoupling capacitors C3 and C4, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
C
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
OWER AND
LOCK
T
RACES AND
G
ROUNDING
CCA
pin as possible.
T
ERMINATION
U1
F
IGURE
C1
C4
6B. PCB B
www.idt.com
OARD
D
PIN 2
PIN 1
50 Ohm
Traces
IFFERENTIAL
11
L
AYOUT FOR
C3
C
The crystal X1 should be located as close as possible to the pins
4 (XTAL_IN) and 5 (XTAL_OUT). The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted para-
sitic inductance and capacitance. Other signal traces should not
be routed near the crystal traces.
X1
RYSTAL
• The differential 50Ω output traces should have the
• Avoid sharp angles on the clock trace. Sharp angle
• Keep the clock traces on the same layer. Whenever pos-
• To prevent cross talk, avoid routing other signal traces in
• Make sure no other signal traces are routed between the
• The matching termination resistors should be located as
700MH
same length.
turns cause the characteristic impedance to change on
the transmission lines.
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
clock trace pair.
close to the receiver input pins as possible.
C11
R7
C16
ICS84330-02
LVPECL F
VCCA
Z
, L
OW
J
C2
ITTER
REQUENCY
GND
Signals
Traces
VCC
VCCA
VIA
ICS84330-02
, C
RYSTAL
S
YNTHESIZER
REV. B JULY 25, 2010
-
TO
-3.3V