MK2069-03GITR

Manufacturer Part NumberMK2069-03GITR
DescriptionIC VCXO CLK TRANSLATOR 56-TSSOP
ManufacturerIDT, Integrated Device Technology Inc
TypeClock Synchronizer
MK2069-03GITR datasheet
 

Specifications of MK2069-03GITR

PllYesInputLVCMOS
OutputLVCMOSNumber Of Circuits1
Ratio - Input:output1:3Differential - Input:outputNo/No
Frequency - Max160MHzDivider/multiplierYes/No
Voltage - Supply3.15 V ~ 3.45 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case56-TSSOP
Frequency-max160MHzLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION MK2069-03
Description
The MK2069-03 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation and frequency
translation. It can accept an input clock over a wide range of
frequencies and produces a de-jittered, low phase noise
clock output. The device is optimized for user configuration
by providing access to all major PLL divider functions. No
power-up programming is needed as configuration is pin
selected. External VCXO loop filter components provide an
additional level of performance tailoring.
The MK2069-03 features a very wide range VCXO PLL
feedback divider, allowing high frequency multiplication
ratios and therefore the input of very low input reference
frequencies. The lock detector (LD) output serves as a
clock status monitor. The clear (CLR) input enables rapid
synchronization to the phase of a newly selected input
clock, while eliminating the generation of extra clock cycles
and wander caused by memory in the PLL feedback divider.
CLR also serves as a temporary holdover function when
kept low.
Block Diagram
IS E T
L F
L F R
P hase
D etector
IC L K
C harge
P um p
F V D iv id e r
1 to 4 0 9 6
V C X O
P L L
C L R
IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 1
Features
Wide range VCXO PLL feedback divider allows high
frequency multiplication ratios and the input of very low
input reference frequencies
Input clock frequency of <1kHz to 13.5MHz
Output clock frequency of 500kHz to 160MHz
PLL lock status output
VCXO-based clock generation offers very low jitter and
phase noise generation, even with low frequency or jittery
input clock.
PLL Clear function (CLR input) allows the VCXO to
free-run, offering a short term holdover function.
2nd PLL provides frequency translation of VCXO PLL to
higher or alternate output frequencies.
Device will free-run in the absence of an input clock (or
stopped input clock) based on the VCXO frequency
pulled to minimum frequency limit.
Low power CMOS technology
56 pin TSSOP package
Single 3.3V power supply
P u lla b le
x ta l
S V 2 :0
R T 1 :0
3
2
X 1
X 2
S V
R T
D iv id e r
V C X O
D iv id e r
1 ,2 ,4 ,6 ,8 ,
1 to 4
1 0 ,1 2 ,1 6
F P V D iv id e r
2 to 6 5
L o c k D e te c to r
12
6
L D C
F V 1 1 :0
F P V 5 :0
DATASHEET
S T 1 :0
2
S T
V C O
D iv id e r
2 ,4 ,8 ,1 6
F T D iv id e r
1 to 6 4
T ra n s la to r
P L L
L D R
6
F T 5 :0
G N D
MK2069-03
V D D
4
V C L K
O E V
T C L K
O E T
R C L K
O E R
L D
O E L
4
REV J 030906

MK2069-03GITR Summary of contents

  • Page 1

    ... External VCXO loop filter components provide an additional level of performance tailoring. The MK2069-03 features a very wide range VCXO PLL feedback divider, allowing high frequency multiplication ratios and therefore the input of very low input reference frequencies. The lock detector (LD) output serves as a clock status monitor ...

  • Page 2

    ... Notes Translator PLL Scaling Divider Selection Table ST1 ST0 VCXO AND SYNTHESIZER Notes 2 For FV addresses 0 to 4094 Divide = Address + 2 : 4096 1 SV Divider Ratio Divider Ratio Divider Ratio Notes 2 For FT addresses Divide = Address + Divider Ratio MK2069-03 REV J 030906 ...

  • Page 3

    ... Ground Ground connection for internal digital circuitry. Power Lock detector threshold setting circuit connection. Refer to circuit on page 10. Output VCXO PLL Reference Clock output. Ground Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR). VCXO AND SYNTHESIZER Pin Description MK2069-03 REV J 030906 ...

  • Page 4

    ... SV1 56 SV2 Functional Description The MK2069- PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to an input reference clock. It contains two cascaded PLL’s with user selectable divider ratios. The first PLL is VCXO-based and uses an external pullable crystal as part of the normal “VCO” (voltage controlled oscillator) function of the PLL ...

  • Page 5

    ... MK2069-03 VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION Application Information The MK2069- mixed analog / digital integrated circuit that is sensitive to PCB (printed circuit board) layout and external component selection. Used properly, the device will provide the same high performance expected from a canned VCXO-based hybrid timing device, but at a lower cost ...

  • Page 6

    ... As another general rule, the following relationship should FPV Divider maintained between components C filter: in loop filter in Farads VCXO AND SYNTHESIZER DON'T STUFF 6 Refer to "Crystal Tuning Load 7 Capacitors" Section Optional 11 Crystal Tuning Capacitors XTAL LFR ISET SET and C S MK2069- the loop P REV J 030906 ...

  • Page 7

    ... As can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from ICS, increasing charge pump current (I both bandwidth and damping factor. VCXO AND SYNTHESIZER is to use the filter P should be increased in value until it P 10E+6 Recommended Range of Operation ) increases CP MK2069-03 REV J 030906 is too P ...

  • Page 8

    ... R S SET S FPV Div 2430 1 M 560 2430 1 M 560 k 0 2796 1 M 680 VCXO AND SYNTHESIZER C Loop Loop Passband P BW Damp. Peaking (-3dB) 4 4.0 0.15dB at 1Hz 1.4 1.2dB at 6Hz 4 4.5 0.12dB at 1Hz . It is useful when S MK2069-03 Note REV J 030906 ...

  • Page 9

    ... TCLK is always locked to VCLK regardless of the state of the CLR input. Lock Detection The MK2069-03 includes a lock detection feature that indicates lock status of VCLK relative to the selected input reference clock. When phase lock is achieved (such as following power-up), the LD output goes high. When phase ...

  • Page 10

    ... RLD and CLD components but the LD output will not be used, RLD can remain unstuffed and CLD can be replaced with a resistor (< 10 kohm). Power Supply Considerations As with any integrated clock device, the MK2069-03 has a special set of power supply requirements: • The feed from the system power supply must be filtered for noise that can cause output clock jitter ...

  • Page 11

    ... MK2069-03 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14pF. To achieve this, the layout should use short traces between the MK2069-03 and the crystal. IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 11 Recommended Crystal Parameters: Crystal parameters can be found in application note MAN05 on the IDT web site ...

  • Page 12

    ... In applications that are especially sensitive to noise, such as SONET or G-Bit ethernet transceivers, some or all of the following crystal shielding techniques should be considered. This is especially important when the MK2069-03 is placed near high speed logic or signal traces. The following techniques are illustrated on the Recommended PCB Layout drawing. ...

  • Page 13

    ... CLD* = External capacitor for lock detector circuit *Note: If output LD is not used, RLD and CLD may be (film type) VCXO AND SYNTHESIZER CBD G A CBB G 603 603 603 43 MK2069 603 40 39 RLD G 38 603 37 CLD 36 603 (film type current value 33 omitted. See text on page 10. MK2069-03 G REV J 030906 ...

  • Page 14

    ... LDR pin. Use RCLK as the scope trigger. LDR will produce a negative pulse equal in length to the charge pump pulse. 3.5) Filter leakage can also be caused by the use of improper loop capacitors. Refer to the section titled ‘Loop Filter Capacitor Type’ on page 9. /20 MK2069-03 REV J 030906 ...

  • Page 15

    ... VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2069-03. These ratings, which are standard values for IDT industrial rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied ...

  • Page 16

    ... VDD, providing utility in hot-plug line card IH VCXO AND SYNTHESIZER Min. Typ. Max. Units 3.15 3.3 3. VDD + V 0.4 -0.4 0.8 V 200 k VDD/2+1 VDD + V 0.4 VDD/2+1 5.5 V -0.4 VDD/2-1 V -10 +10 A -10 + VDD-0.4 V 2.4 V 0.4 V ±50 mA ± VDD V MK2069-03 REV J 030906 ...

  • Page 17

    ... OH C =15pF L t 0.8 to 2.0V, C =15pF 2.0 to 0.8V, C =15pF OF L VCXO AND SYNTHESIZER Min. Typ. Max. Units 13.5 27 MHz ±115 ±150 ppm -300 -150 ppm 0.001 27 MHz 10 nsec 0 320 MHz 105 2.5 160 MHz 0.5 VCLK Period 1 1 MK2069-03 REV J 030906 ...

  • Page 18

    ... IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 18 Symbol Conditions t 0.8 to 2.0V, C =15pF 2.0 to 0.8V, C =15pF Rising edges, C =15pF Rising edges, C =15pF Rising edges, C =15pF OUT VCXO AND SYNTHESIZER Min. Typ. Max. Units 0. 0. 2 1.5 + MK2069-03 REV J 030906 ...

  • Page 19

    ... Marking MK2069-03GI MK2069-03GI MK2069-03GITR MK2069-03GI While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied ...

  • Page 20

    ... MK2069-03 VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc ...