IDT82V3280PFG8 IDT, Integrated Device Technology Inc, IDT82V3280PFG8 Datasheet - Page 125

• Manufacturer Part Number: IDT82V3280PFG8
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG8

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG8

T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration
Programming Information
IDT82V3280
Address: 58H
Type: Read / Write
Default Value: 01101011
T0_DPLL_LOCK
ED_DAMPING2
7 - 5
4 - 0
Bit
7
T0_DPLL_LOCKED_DAMPING[2:0]
T0_DPLL_LOCKED_BW[4:0]
T0_DPLL_LOCK
ED_DAMPING1
6
Name
T0_DPLL_LOCK
ED_DAMPING0
5
These bits set the locked damping factor for T0 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
011: 5. (default)
100: 10.
101: 20.
110, 111: Reserved.
These bits set the locked bandwidth for T0 DPLL.
00000: 0.5 mHz.
00001: 1 mHz.
00010: 2 mHz.
00011: 4 mHz.
00100: 8 mHz.
00101: 15 mHz.
00110: 30 mHz.
00111: 60 mHz.
01000: 0.1 Hz.
01001: 0.3 Hz.
01010: 0.6 Hz.
01011: 1.2 Hz. (default)
01100: 2.5 Hz.
01101: 4 Hz.
01110: 8 Hz.
01111: 18 Hz.
10000: 35 Hz.
10001: 70 Hz.
10010: 560 Hz.
10011 ~ 11111: Reserved.
T0_DPLL_LOC
KED_BW4
4
125
T0_DPLL_LOC
KED_BW3
3
Description
T0_DPLL_LOC
KED_BW2
2
T0_DPLL_LOC
KED_BW1
1
December 9, 2008
T0_DPLL_LOC
KED_BW0
0
WAN PLL