IDT82V3280PFG8 IDT, Integrated Device Technology Inc, IDT82V3280PFG8 Datasheet - Page 72

• Manufacturer Part Number: IDT82V3280PFG8
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG8

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG8

MS_SL_CTRL_CNFG - Master Slave Control
PROTECTION_CNFG - Register Protection Mode Configuration
Programming Information
IDT82V3280
Address: 13H
Type: Read / Write
Default Value: XXXXXXX0
Address: 7EH
Type: Read / Write
Default Value: 10000101
PROTECTION_
7 - 0
Bit
7-1
Bit
0
DATA7
7
7
-
PROTECTION_DATA[7:0]
MS_SL_CTRL
PROTECTION_
Name
Name
-
DATA6
6
6
-
Reserved.
These bits, together with the MS/ SL pin, control whether the device is configured as the Master or as the Slave.
The default value of this bit is ‘0’.
PROTECTION_
These bits select a register write protection mode.
00000000 - 10000100, 10000111 - 11111111: Protected mode. No other registers can be written except this register.
10000101: Fully Unprotected mode. All the writable registers can be written. (default)
10000110: Single Unprotected mode. One more register can be written besides this register. After write operation (not
including writing a ‘1’ to clear the bit to ‘0’), the device automatically switches to Protected mode.
MS/ SL pin
DATA5
High
Low
5
5
-
Master/Slave Control
PROTECTION_
DATA4
MS_SL_CTRL Bit
4
4
-
0
1
0
1
72
PROTECTION_
DATA3
3
3
-
Description
Description
PROTECTION_
DATA2
Result
Master
Master
Slave
Slave
2
2
-
PROTECTION_
DATA1
1
1
-
December 9, 2008
PROTECTION_
MS_SL_CTRL
DATA0
0
0
WAN PLL