SI4134T-BM Silicon Laboratories Inc, SI4134T-BM Datasheet
SI4134T-BM
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SI4134T-BM Summary of contents
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... RFIPP Si4201- GND 1 15 SDO RXQP 2 14 PDN GND RXQN 3 13 XEN PAD RXIP 4 12 ION RXIN 5 11 IOP Si4134T- IFLB 1 24 GND IFLA PDN 3 22 GND XDRVEN 4 21 RFLC GND PAD XDRV 5 20 RFLD GND 6 19 GND VDD 7 18 ...
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Aero+ 2 Rev. 1.2 ...
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... DCXO Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 XDRV Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 XOUT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Descriptions: Si4200- .38 Pin Descriptions: Si4200DB- Pin Descriptions: Si4201- .40 Pin Descriptions: Si4134T- Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Package Outline: Si4200-BM and Si4200DB- Package Outline: Si4201- .44 Package Outline: Si4134T- Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Rev. 1.2 ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The Si4200 and Si4134T devices are high-performance RF integrated circuits with an ESD rating of < 2 kV. Handling and assembly of these devices should only be done at ESD-protected workstations. ...
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... Table 3. DC Characteristics (V = 2 – ° Parameter Si4200 Supply Current 1 Si4201 Supply Current 2 Si4134T Supply Current Total Chipset Supply Current 3 High Level Input Voltage 3 Low Level Input Voltage 3 High Level Input Current 3 Low Level Input Current 4 High Level Output Voltage ...
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Aero+ Table 4. AC Characteristics (V = 2 – ° Parameter SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time PDN Rise Time PDN Fall ...
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D17 D16 SDI 50% 20 HOLD 80% SCLK 50% 20 EN1 CLK 80% SEN 50% 20% Figure 3. Serial Interface Write Timing Diagram 80% A0 SDI 50% 20% 80% SDO ...
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Aero+ Table 5. Receiver Characteristics (V = 2 – ° Parameter 1 GSM Input Frequency 1 DCS or PCS Input Frequency 2,3 Noise Figure ° 2,3 Noise Figure ...
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... Offsets can be measured and calibrated out. See ZERODEL[2:0] in the register description. 11. Group delay is measured from antenna input to baseband outputs. Differential group delay is measured in-band. 12. Includes settling time of the Si4134T frequency synthesizer with 13 MHz DCXO output settled. Settling to 5 degrees phase error measured at RXIP, RXIN, RXQP, and RXQN pins. ...
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Aero+ −20 −40 −60 −80 −100 −120 Figure 5. Receive Path Magnitude Response (CSEL = −2 −4 −6 −8 −10 −12 −14 −16 Figure 6. Receive Path Passband Magnitude Response (CSEL = ...
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Receive Path Magnitude Response (CSEL = 1) 0 −20 −40 −60 − 100 150 Figure 8. Receive Path Magnitude Response (CSEL = 1) Receive Path Passband Magnitude Response (CSEL = −2 −4 −6 −8 −10 ...
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Aero+ Table 6. Transmitter Characteristics (V = 2 – ° Parameter 1 RFOG Output Frequency 2 RFOD Output Frequency 3,4 I/Q Differential Input Swing 3 I/Q Input Common-Mode 3,4 I/Q Differential ...
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... MHz measured with 100 kHz RBW. 7. Measured with all 1s pattern. 8. Including settling time of the Si4134T frequency synthesizer with 13 MHz DCXO output settled. Settling time measured at the RFOD and RFOG pins to 0.1 ppm frequency error. Symbol Test Condition 2nd harmonic ...
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Aero+ Table 7. Frequency Synthesizer Characteristics (V = 2 – ° Parameter 1 RF1 VCO Frequency 1 RF2 VCO Frequency 1 IF VCO Frequency RF1 PLL Phase Detector Update Frequency IF ...
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... For the GSM input, the RF1 VCO is divided by two on the Si4200. During transmit, the IF VCO is divided by two on the Si4200. These tuning ranges are guaranteed provided the VCOs on the Si4134T are properly centered during the PC board design phase. See “AN49: Aero Transceiver PCB Layout Guidelines” for more information. ...
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... RFIPP VDD VDD VDD C12 IFLB GND 2 23 IFLA PDN GND 4 21 XDRVEN RFLC XDRV RFLD VDD SI4134T 6 19 GND GND 7 18 VDD SDO 8 17 GND SDI C11 X1 13/26MHz Rev. 1.2 EGSM TX Output DCS/PCS TX Output Z1 C1 EGSM RX Input OUT OUT+ Gnd C2 ...
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... Murata LQW15A series (0402 size) Murata LQW18AN series (0603 size) Murata LQW15A series (0402 size) Multi-layer (0402 or 0603 size) PCB Trace Silicon Laboratories Si4200-BM Silicon Laboratories Si4201-BM Silicon Laboratories Si4134T-BM = 8.0 pF KDS BR13000AA0E L KSS CX96FFFBQAJ13 EPCOS B39881-B7719-C610 (6-pin, 2.0x2.5 mm) EPCOS B39881-B9001-C710 (5-pin, 1.4x2.0 mm) Murata SAFSD881MFL0T00R00 (6-pin, 2 ...
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... RF front end for multi-band GSM/GPRS digital cellular handsets and wireless data modems. The chipset consists of the Si4200 GSM transceiver, Si4201 universal baseband interface, and Si4134T dual RF synthesizer with an integrated digitally-controlled crystal oscillator (DCXO). The highly integrated solution eliminates the IF SAW filter, external low noise ...
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... LNAG[1:0] and LNAC[1:0] bits in register 05h. A quadrature image-reject mixer downconverts the RF signal to a 100 kHz intermediate frequency (IF) with the RFLO from the Si4134T frequency synthesizer. The RFLO frequency is between 1737.8 and 1989.9 MHz, and is divided by two in the Si4200 for GSM 850 and E- ...
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... TXVCO is centered between the DCS 1800 and PCS 1900 bands, and its output is divided by two for the GSM 850 and E-GSM 900 bands. The Si4134T generates the RFLO frequency between 1272 and 1483 MHz. To allow a single VCO to be used for the ...
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... I/O SEN SDO Figure 14. Si4134T Frequency Synthesizer Block Diagram The Si4134T dual frequency synthesizer is a monolithic CMOS integrated circuit that performs IF and RF synthesis. An integrated digitally-controlled crystal oscillator (DCXO) is provided to generate the reference clock. The DCXO allows the use of a standard crystal resonator, avoiding the need for a crystal oscillator module ...
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... VAR PLL Determining L EXT The center frequencies for the RF2, and IF VCOs in the Si4134T are set using an external inductance (L is very important that L be properly designed to EXT ensure maximum manufacturing margin for the desired VCO frequency tuning ranges. Because the total tank ...
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... DCXO Overview The Si4134T integrates the DCXO circuitry required to generate a precise system reference clock using only an external crystal resonator. (See Figure 16.) An internal digitally programmable capacitor array (CDAC) provides a coarse method of adjusting the reference frequency in discrete steps. An integrated analog varactor (CVAR) allows for a fine and continuous adjustment of the reference frequency by an external control voltage (XAFC) ...
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... SDO pin after writing the revision register with the address to be read. SDO is enabled when PDN = 0 on the Si4201 and when PDN = 1 on the Si4134T, allowing the SDO pin to be shared. Writing to any of the registers causes the function of SDO to revert to its previously programmed function ...
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... Reserved 20h RX Master #1 RXBAND[1:0] 21h RX Master #2 0 DPDS[2:0] 22h RX Master # 23h TX Master #1 TXBAND[1:0] 24h TX Master #2 FIF[3:0] 28h CDAC 30h Si4134T Revision/Read 31h Config 32h Powerdown 33h RF1 N Divider 0 0 34h RF2 N Divider 0 0 35h IF N Divider 0 0 Notes: 1. Any register not listed here is reserved and should not be written. Writing to reserved registers may result in unpredictable behavior ...
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... Function Program to zero. Chip Reset Normal operation (default Reset all registers to default values. Note: See “Control Registers” on page 25 for more details. This register must be written to 0 twice after a reset operation. This bit does not reset Si4134T registers 30h to 35h. Rev. 1 ...
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Register 02h. Mode Control (Si4200/Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:3 Reserved 2 AUTO 1:0 MODE[1:0] Note: Calibration must be performed each time the power supply is applied. ...
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Aero+ Register 03h. Configuration (Si4200) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name DIAG[1:0] Bit Name 17:14 Reserved 13:12 DIAG[1:0] 11 SWAP 10:8 Reserved 7:6 TXBAND[1:0] 5:4 RXBAND[1:0] 3:2 Reserved 1 Reserved 0 Reserved ...
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Register 04h. Transmit Control (Si4200) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:11 Reserved 10 Reserved 9:8 BBG[1:0] 7:4 FIF[3:0] 3:0 Reserved BBG[1:0] ...
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Aero+ Register 05h. Receive Gain (Si4200/Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:14 Reserved 13:8 DGAIN[5:0] 7 Reserved 6:4 AGAIN[2:0] 3:2 LNAC[1:0] 1:0 LNAG[1: DGAIN[5:0] ...
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Register 10h. Revision/Read (Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:8 Reserved 7:0 REV1[7:0] Note: Registers on the Si4201 can be read by writing this register with the address ...
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Aero+ Register 12h. DAC Configuration (Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:11 Reserved 10 Reserved 9 XBUF 8 Reserved 7 ZDBS 6:4 ZERODEL[2:0] 3:2 DACCM[1:0] 1:0 DACFS[1:0] 32 ...
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Register 19h. Reserved (Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:0 Reserved Register 20h. RX Master #1 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name RXBAND[1:0] Notes: ...
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... Reserved 5:0 CDAC[5:0] Register 30h. Revision/Read (Si4134T) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:8 Reserved 7:0 REV3[7:0] Note: Registers on the Si4134T can be read by writing this register with the address of the register to be read [13: Function Read as zero ...
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... Register 31h. Main Configuration (Si4134T) Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name SDOSEL[3:0] Bit Name 17:15 Reserved 14:11 SDOSEL[3:0] 10:5 Reserved 4 RFUP 3 DIV2 2:0 Reserved Function Program to zero. SDO Output Control Register. The mux_output table is as follows: 0000 Connected to the Output Shift Register (default). ...
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... Bit Name 17:16 Reserved Program to zero. 15:0 N [15:0] N Divider for RF PLL (RF1 VCO). RF1 Used for Receive mode. Register 34h. RF2 N Divider (Si4134T) Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name 0 0 Bit Name 17:16 Reserved Program to zero. 15:0 ...
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... Register 35h Divider (Si4134T) Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name 0 0 Bit Name 17:16 Reserved Program to zero. 15:0 N [15:0] N Divider for IF Synthesizer. IF Used for transmit mode [15:0] IF Function Rev. 1.2 Aero ...
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Aero+ Pin Descriptions: Si4200-BM Pin Number(s) Name 1, 2 ION, IOP 3, 4 CKN, CKP 5, 6 TXIP, TXIN 7, 8 TXQP, TXQN 9, 10 IFLOP, IFLON 11, 27, 30, GND GND pad 12, 13 RFLOP, RFLON 14, 23, 26, ...
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... Data output to Si4201 (differential). Clock input from Si4201 (differential). Transmit I input (differential). Transmit Q input (differential). IFLO Input from Si4134T (differential). RFLO Input from Si4134T (differential). Supply voltage. Diagnostic output. Can be used as digital outputs to control antenna switch functions. PCS LNA input (differential). ...
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Aero+ Pin Descriptions: Si4201-BM Pin Number(s) Name 2, 3 RXQP, RXQN 4, 5 RXIP, RXIN XIN 9, 10 CKP, CKN 11, 12 IOP, ION 13 XEN 14 PDN 15 SDO 16 SEN 17 SCLK 18 ...
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... Pin Descriptions: Si4134T-BM Pin Number(s) Name 1, 2 IFLB, IFLA 3 PDN 4 XDRVEN 5 XDRV XTAL1 12 XTAL2 13 XTALEN 14 XAFC 15 SEN 16 SCLK 17 SDI 18 SDO 20, 21 RFLC, RFLD 26, 27 RFLON, RFLOP RF PLL output to Si4200 (differential). 29, 30 IFLON, IFLOP 6, 8, 19, 22, 24, GND 25, 32, GND pad 32 31 ...
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... GSM 850/PCS 1900 or E-GSM 900/DCS 1800 Si4201-BM Universal Baseband Interface Si4201-GM Universal Baseband Interface Si4134T-BM Dual RF Synthesizer with DCXO Si4134T-GM Dual RF Synthesizer with DCXO *Note: Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. ...
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Package Outline: Si4200-BM and Si4200DB-BM Figure 18 illustrates the package details for the Si4200-BM and Si4200DB-BM. Table 12 lists the values for the dimensions shown in the illustration PIN1 ID 0.50 DIA Top View ...
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Aero+ Package Outline: Si4201-BM Figure 19 illustrates the package details for the Si4201-BM. Table 13 lists the values for the dimensions shown in the illustration PIN1 ID 0.50 DIA Top View Figure 19. 20-Pin ...
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... Package Outline: Si4134T-BM Figure 18 illustrates the package details for the Si4134T-BM. Table 12 lists the values for the dimensions shown in the illustration PIN1 ID 0.50 DIA Top View Figure 20. 32-Pin Micro Leadframe Package (MLP) Symbol Millimeters Min Nom A — 0.85 A1 0.00 0.01 A2 — ...
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... Updated device weight. Added notes 5 and 6. Revision 1.1 to Revision 1.2 This document corresponds to the following: Si4200DB revision E (dual band LNA) or Si4200 revision F (triple band LNA) Si4201 revision C Si4134T revision A "Package Outline: Si4134T-BM" on page 45 (documentation change only, no change to part) Updated L dimension 46 Rev. 1.2 ...
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Notes: Rev. 1.2 Aero+ 47 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and Aero are trademarks of Silicon Laboratories Inc. Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holder 48 Rev ...