SI4134T-BM Silicon Laboratories Inc, SI4134T-BM Datasheet - Page 18

• Manufacturer Part Number: SI4134T-BM
• Description: IC RF SYNTH DUAL W/DCXO 32MLP
• Manufacturer: Silicon Laboratories Inc
• Series: Aero™+r
• Type: Frequency Synthesizerr

Specifications of SI4134T-BM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/Yes
• Frequency - Max: 1.99GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1.99GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Aero+
Functional Description
The Aero+ transceiver is the industry’s most integrated
RF front end for multi-band GSM/GPRS digital cellular
handsets and wireless data modems. The chipset
consists of the Si4200 GSM transceiver, Si4201
universal baseband interface, and Si4134T dual RF
synthesizer with an integrated digitally-controlled crystal
oscillator (DCXO). The highly integrated solution
eliminates the IF SAW filter, external low noise
amplifiers (LNAs) for three bands, transmit and RF
voltage-controlled oscillator (VCO) modules, and more
than
conventional designs.
The high level of integration combined with micro
leadframe package (MLP) technology and fine line
CMOS process technology results in a solution with
50% less area and 80% fewer components than
competing solutions. A triple-band GSM transceiver
using the Aero+ chipset can be implemented with 19
components in less than 2 cm
of integration is an enabling force in lowering the cost,
simplifying the design and manufacturing, and shrinking
the form factor in next-generation GSM/GPRS voice
and data terminals.
The receive section uses a digital low-IF architecture
that avoids the difficulties associated with direct
conversion while delivering lower solution cost and
18
60
other
GSM
GSM
DCS
PCS
DCS
PCS
discrete
PA
PA
2
components
Figure 11. Aero+ Transceiver Block Diagram
of board area. This level
LNA
LNA
LNA
0 / 90
found
PLL
RF
Rev. 1.2
in
PGA
PGA
DET
PLL
IF
φ
reduced complexity. The universal baseband interface
is compatible with any supplier’s baseband subsystem.
The transmit section is a complete up-conversion path
from the baseband subsystem to the power amplifier,
and uses an offset phase-locked loop (PLL) with a fully
integrated transmit VCO. The frequency synthesizer
uses Silicon Laboratories’ proven technology that
includes integrated RF and IF VCOs, varactors, and
loop filters.
The unique integer-N PLL architecture used in the
Si4134T produces a transient response superior in
speed to fractional-N architectures without suffering the
high phase noise or spurious modulation effects often
associated with those designs. This fast transient
response makes the Aero+ chipset well suited to GPRS
multi-slot applications where channel switching and
settling times are critical.
While conventional solutions use BiCMOS or other
bipolar process technologies, the Aero+ chipset is the
industry’s first cellular transceiver to be implemented in
a 100% CMOS process. This brings the cost savings
and extensive manufacturing capacity of CMOS to the
GSM market.
Si4134T
Si4200
DCXO
ADC
ADC
100 kHz
PGA
PGA
Si4201
DAC
DAC
XOUT
AFC
Q
Q
I
I