IDT5V9885NLGI8 IDT, Integrated Device Technology Inc, IDT5V9885NLGI8 Datasheet - Page 23

• Manufacturer Part Number: IDT5V9885NLGI8
• Description: IC CLK GEN 3.3V EEPROM 28-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of IDT5V9885NLGI8

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN, 28-VFQFPN
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 5V9885NLGI8

1 2 3 4
1 2 3 4
1 2 3 4
EXTERNAL I
PROGWRITE
PROGREAD
prior to a read operation by issuing the following command:
KEY:
SYMBOLS:
the Progread command):
IDT5V9885
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a known "read" register address
Note: Figure 4b above by itself is the Progread command format. The ID byte for the 5V9885 is 10hex. Each byte recieved increments the register address.
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave acknowledgement bit (i.e., followed by
From Master to Slave
From Master to Slave, but can be omitted if followed by the correct sequence
Normally data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a repeated START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
ACK - Acknowledge (SDA LOW)
NACK - Not Acknowledge (SDA HIGH)
Sr - Repeated Start Condition
S - START Condition
P - STOP Condition
Sr Address
S
2
C INTERFACE CONDITION
7-bits
Address
7-bits
S
R/W
1
Address
7-bits
R/W
0
ACK ID Byte
1-bit
1-bit
ACK Command Code
Figure 4a: Prior to Progread Command Set Register Address
R/W
0
8 bits
8-bits: xxxxxx00
1-bit
ACK Command Code
Figure 4b: Progread Command Frame
Figure 3: Progwrite Command Frame
ACK
1-bit
8-bits: xxxxxx00
Data_1
8-bits
23
ACK
1-bit
ACK
1-bit
ACK
1-bit
Register
Data_2
8-bits
8-bits
Register
8-bits
ACK
1-bit
1-bit
ACK
INDUSTRIAL TEMPERATURE RANGE
Data_last
1-bit
ACK
8-bits
8-bits
Data
P
ACK
1-bit
NACK
1-bit
P
P