IDT5V9885NLGI8 IDT, Integrated Device Technology Inc, IDT5V9885NLGI8 Datasheet - Page 32

• Manufacturer Part Number: IDT5V9885NLGI8
• Description: IC CLK GEN 3.3V EEPROM 28-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of IDT5V9885NLGI8

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN, 28-VFQFPN
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 5V9885NLGI8

RAM (PROGRAMMING REGISTER) TABLES
IDT5V9885
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
ADDR
0x0B
0x0C
0x0D
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
7
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
(Default Settings)
5
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT #
3
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Hex Value
Register
Default
FF
00
30
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
40
00
ODIV0_CONFIG0
ODIV0_CONFIG1
ODIV0_CONFIG2
ODIV0_CONFIG3
SP
7
CP0[3:0]_CONFIG0
CP0[3:0]_CONFIG1
CP0[3:0]_CONFIG2
CP0[3:0]_CONFIG3
A0[3:0]_CONFIG0
A0[3:0]_CONFIG1
A0[3:0]_CONFIG2
A0[3:0]_CONFIG3
OKC
SH
6
IP0[2:0]_CONFIG0
IP0[2:0]_CONFIG1
IP0[2:0]_CONFIG2
IP0[2:0]_CONFIG3
GINEN5
OE6
OS6
5
XDRV[1:0]
D0[7:0]_CONFIG0
D0[7:0]_CONFIG1
D0[7:0]_CONFIG2
D0[7:0]_CONFIG3
N0[7:0]_CONFIG0
N0[7:0]_CONFIG1
N0[7:0]_CONFIG2
N0[7:0]_CONFIG3
GINEN4
XTALCAP[7:0]
OE5
OS5
4
BIT #
GINEN3
OE4
OS4
3
GINEN2
PLLS2
RZ0[3:0]_CONFIG0
RZ0[3:0]_CONFIG1
RZ0[3:0]_CONFIG2
RZ0[3:0]_CONFIG3
CZ0[3:0]_CONFIG0
CZ0[3:0]_CONFIG1
CZ0[3:0]_CONFIG2
CZ0[3:0]_CONFIG3
N0[11:8]_CONFIG0
N0[11:8]_CONFIG1
N0[11:8]_CONFIG2
N0[11:8]_CONFIG3
OE3
OS3
2
32
GINEN1
PLLS1
OE2
OS2
1
GINEN0
PLLS0
MFC
OE1
OS1
0
MFC=Manual Frequency Control Mode ('0'=All PLL Control (Default), "1"=PLL0 Control Only );
GINEN0 to GINEN5=GINx Pins Enable Bits, ("1"=Enable (Default), "0"=No Connect (Internal State will be "Low"));
Address 0x04, Bits[7:1] are reserved and should bet set to "0".
Address 0x05, Bits 7, 6 are reserved and should be set to "1'.
XDRV=crystal drive strength ("00" = 1.4V, "01" = 2.3V, "10"= 3.2V pk-pk swing typical, "11"=XTAL_IN with external clock-default); When
"11", XTALCAP[7:0] value must also be set to "0".
Bits 7,6, 3, 2, 1, 0 are reserved and should be set to "0"
XTAL load cap = 3.5pF+ (0.125 x XTALCAP[7:0]) , 3.5pF to 35.4pF; Each XTAL pin to GND;
(For example, "00000001"=0.125pF, "00000010"=0.25pF, "00000100"=0.5pF); Default = "00000000";
PLL0 LOOP FILTER SETTING
Loop Filter Values for PLL0 - For 4 Configurations (Default value is '0');
CONFIG0 will be selected if GINx are disabled and operating in MFC mode
ODIV0_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated
with PLL0; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;
Resistor = 0.3KΩ + RZ0[3:0] * 1KΩ, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);
Zero capacitor = 6pF + CZ0[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);
Pole capacitor = 1.3pF + CP0[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)
Charge pump current = 5 * 2^IP0[2:0] μA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;
PLL0 INPUT DIVIDER D0 SETTING
PLL0 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');
PLL0 MULTIPLIER SETTING
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
N0[11:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
A0[3:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
SSC_OFFSET0[5:0] - Spread Spectrum Fractional Multiplier Offset Value. See Spread Spectrum Settings in register address range
0x60-0x67
Total Multiplier Value M0 = 2 * N0[11:0] + A0 + 1 + SS_OFFSET0 * 1/64
When A0[3:0] = 0 and spread spectrum disabled, M0= 2 * N0[11:0];
When A0[3:0] > 0 and spread spectrum disabled, M0 = 2 * N0[11:0] + A0 + 1;
(Note: A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);
SP=Shutdown/OE Polarity for SHUTDOWN/OE signal pin, ("0"= Active High (Default), "1"= Active Low);
OEx=Output Disable Function for OUTx, ("1"=OUTx disabled based on OE pin (Default for OUT2-6, Disable mode is defined by OEMx
bits), "0"= Outputs enabled and no association with OE pin (Default));
OSx=Output Power Suspend function for OUTx, ("1"=OUTx will be suspended on GIN3/SUSPEND pin (MFC="1"), "0"= Always Enabled
(Default));
PLLSx=Determines which PLLx to suspend when GIN3 is programmed to be used as SUSPEND, It suspends all the outputs associated
with that PLL, ("1"= suspends based on SUSPEND pin, "0"= PLL enabled and no association with SUSPEND pin (Default)); It over-rides
OSx bits;
SH=Determines the function of the SHUTDOWN/OE signal pin. ("1"=Global Shutdown; this over-rides OEx and OSx bits, "0"=Ouput
Enable/Disable (Default))
OKC=clock OK count, "0"=8 cycles, "1"=1024 cycles (Default) of Input Clocks for Revertive Switchover Mode:
Address 0x1D, Bit 7; Address 0x1E, Bits [7:3] are reserved and should be set to "0"
Reserved Bits. Should be ignored in programming
INDUSTRIAL TEMPERATURE RANGE
No Register Exists
DESCRIPTION