IDT5V9885NLGI8 IDT, Integrated Device Technology Inc, IDT5V9885NLGI8 Datasheet - Page 25

• Manufacturer Part Number: IDT5V9885NLGI8
• Description: IC CLK GEN 3.3V EEPROM 28-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of IDT5V9885NLGI8

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN, 28-VFQFPN
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 5V9885NLGI8

NOTE:
1. Guaranteed by design.
JTAG
AC ELECTRICAL CHARACTERISTICS
of an interrupt of some sort such as a power down of the part in the middle of a save or restore operation, the contents to or from the EEPROM will be partially
loaded, and a CRC error will be generated. The CERR bit (0x81) will be asserted to indicate that an error has occurred. The LOSS_LOCK signal will also
be asserted.
will not function properly if the device is in shutdown mode (SHUTDOWN pin asserted). The IDT5V9885 will be ready to accept a programming instruction once
it acknowledges its 7-bit I
NOTE:
t1 = t
t2 = t
t3 = t
t4 = t
t5 = t
t6 = t
IDT5V9885
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Symbol
t
t
t
t
TCLKHIGH
TCLKLOW
TCLKRISE
TCLKFALL
In order for the save and restore instructions to function properly, the IDT5V9885 must not be in shutdown mode (SHUTDOWN pin asserted). In the event
On power-up of the IDT5V9885, an automatic restore is performed to load the EEPROM contents into the internal programming registers. The auto-restore
t
t
t
TCLK
TCLKLOW
RSR
TCLKHIGH
TCLKFALL
RST
TCLKRISE
RST
RSR
(reset pulse width)
(reset recovery)
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
JTAG Reset Recovery
2
C address.
TCLK
TDI/TMS
TDO
TRST
t3
t5
Min.
100
40
40
—
—
50
50
t1
t4
t
t6
Max.
DS
5
5
—
—
—
—
—
t
(1)
(1)
TCLK
t
DH
Standard JTAG Timing
Units
t2
ns
ns
ns
ns
ns
ns
ns
25
SYSTEM INTERFACE PARAMETERS
NOTE:
1. 50pF loading on external output signals.
Symbol
t
t
DOH
t
t
DO
DS
DH
Parameter
Data Output
Data Output Hold
Data Input, t
Data Input, t
(1)
RISE
FALL
t
DO
= 3ns
= 3ns
(1)
INDUSTRIAL TEMPERATURE RANGE
TDO
Min.
—
10
10
0
Max.
20
—
—
—
Units
ns
ns
ns
ns