LMX2315TM National Semiconductor, LMX2315TM Datasheet - Page 2

• Manufacturer Part Number: LMX2315TM
• Description: IC FREQ SYNTHESIZER 20-TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2315TM

• Pll: Yes
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LMX2315TM

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Pin No.
2,9,12
Connection Diagram
Pin Descriptions
10
11
13
14
15
16
17
18
19
20
1
4
6
7
8
3
5
OSC
OSC
V
V
D
GND
LD
f
CLOCK
DATA
LE
FC
BISW
f
PWDN
NC
Order Number LMX2315TM, LMX2315TMX, LMX2325TM, LMX2325TMX, LMX2320TM or LMX2320TMX
IN
OUT
p
r
P
CC
o
Name
Pin
IN
OUT
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Oscillator input. A CMOS inverting gate input intended for connection to a crystal resonator for
operation as an oscillator. The input has a V
external CMOS or TTL logic gate. May also be used as a buffer for an externally provided
reference oscillator.
Oscillator output.
Power supply for charge pump. Must be
Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors should be
placed as close as possible to this pin and be connected directly to the ground plane.
Internal charge pump output. For connection to a loop filter for driving the input of an external VCO.
Ground.
Lock detect. Output provided to indicate when the VCO frequency is in “lock”. When the loop is
locked, the pin’s output is HIGH with narrow low pulses.
Prescaler input. Small signal input from the VCO.
High impedance CMOS Clock input. Data is clocked in on the rising edge, into the various counters
and registers.
Binary serial data input. Data entered MSB first. LSB is control bit. High impedance CMOS input.
Load enable input (with internal pull-up resistor). When LE transitions HIGH, data stored in the shift
registers is loaded into the appropriate latch (control bit dependent). Clock must be low when LE
toggles high or low. See Serial Data Input Timing Diagram.
Phase control select (with internal pull-up resistor). When FC is LOW, the polarity of the phase
comparator and charge pump combination is reversed.
Analog switch output. When LE is HIGH, the analog switch is ON, routing the internal charge pump
output through BISW (as well as through D
Monitor pin of phase comparator input. CMOS output.
Output for external charge pump.
resistor.
Power Down (with internal pull-up resistor).
PWDN = HIGH for normal operation.
PWDN = LOW for power saving.
Power down function is gated by the return of the charge pump to a TRI-STATE
Output for external charge pump.
No connect.
20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM)
See NS Package Number MTC20
LMX2315/LMX2320/LMX2325
2
p
r
is a CMOS logic output.
is an open drain N-channel transistor and requires a pull-up
V
o
Description
).
CC
DS012339-2
CC
.
/2 input threshold and can be driven from an
®
condition.