M48T37Y-70MH6F STMicroelectronics, M48T37Y-70MH6F Datasheet - Page 8

• Manufacturer Part Number: M48T37Y-70MH6F
• Description: IC TIMEKPR NVRAM 256KB 5V 44-SOH
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T37Y-70MH6F

• Memory Size: 256K (32K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-SOH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4721-2

Operation modes
2
Note:
2.1
8/30
Operation modes
As
oscillator of the M48T37Y/V are integrated on one silicon chip. The memory locations that
provide user accessible BYTEWIDE™ clock information are in the bytes with addresses
7FF1 and 7FF9h-7FFFh (located in
century, year, month, date, day, hour, minute, and second in 24-hour BCD format.
Corrections for 28, 29 (leap year - valid until the year 2100), 30, and 31 day months are
made automatically.
Byte 7FF8h is the clock control register. This byte controls user access to the clock
information and also stores the clock calibration setting.
Byte 7FF7h contains the watchdog timer setting. The watchdog timer redirects an out-of-
control microprocessor and provides a reset or interrupt to it. Bytes 7FF2h-7FF5h are
reserved for clock alarm programming. These bytes can be used to set the alarm. This will
generate an active low signal on the IRQ/FT pin when the alarm bytes match the date,
hours, minutes, and seconds of the clock. The eight clock bytes are not the actual clock
counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE
memory cells. The M48T37Y/V includes a clock control circuit which updates the clock bytes
with current information once per second. The information can be accessed by the user in
the same manner as any other location in the static memory array.
The M48T37Y/V also has its own power-fail detect circuit. The control circuitry constantly
monitors the single V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
battery backup switchover voltage (V
maintains data and clock operation until valid power returns.
Table 2.
1. See
X = V
READ mode
The M48T37Y/V is in the READ mode whenever WRITE enable (W) is high and chip enable
(E) is low. The unique address specified by the 15 address inputs defines which one of the
32,752 bytes of data is to be accessed. Valid data will be available at the data I/O pins within
address access time (t
and output enable (G) access times are also satisfied. If the E and G access times are not
Deselect
WRITE
READ
READ
Deselect
Deselect
Figure 3 on page 7
Mode
IH
Table on page 23
or V
IL
Operating modes
V
; V
SO
SO
4.5 to 5.5 V
3.0 to 3.6 V
to V
≤ V
= Battery backup switchover voltage.
V
CC
PFD
or
SO
for details.
CC
AVQV
shows, the static memory array and the quartz controlled clock
supply for an out of tolerance condition. When V
(1)
(min)
) after the last address input signal is stable, providing that the E
(1)
Doc ID 7019 Rev 9
Table 5 on page
V
V
V
V
SO
E
X
X
IH
IL
IL
IL
), the control circuitry connects the battery which
V
V
G
X
X
X
X
IH
IL
V
V
V
13). The clock locations contain the
W
X
X
X
IH
IH
IL
DQ0-DQ7
CC
High Z
High Z
High Z
High Z
D
D
OUT
. As V
IN
CC
M48T37Y, M48T37V
Battery backup mode
falls below the
CC
CMOS standby
is out of
Standby
Power
Active
Active
Active