M48T37Y-70MH1E STMicroelectronics, M48T37Y-70MH1E Datasheet - Page 17

IC TIMEKPR NVRAM 256KBIT5V 44SOH

M48T37Y-70MH1E

Manufacturer Part Number
M48T37Y-70MH1E
Description
IC TIMEKPR NVRAM 256KBIT5V 44SOH
Manufacturer
STMicroelectronics
Series
Timekeeper®r
Type
Clock/Calendar/NVSRAMr
Datasheets

Specifications of M48T37Y-70MH1E

Memory Size
256K (32K x 8)
Time Format
HH:MM:SS (24 hr)
Date Format
YY-MM-DD-dd
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-SOH
Bus Type
Parallel
User Ram
32KB
Operating Supply Voltage (typ)
5V
Package Type
SOH
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
44
Mounting
Surface Mount
Memory Configuration
32K X 8
Nvram Features
RTC
Interface Type
Parallel
Access Time
70ns
Supply Voltage Range
4.5V To 5.5V
Memory Case Style
SOIC
No. Of Pins
44
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2854-5
M48T37Y-70MH1

Available stocks

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0
M48T37Y, M48T37V
3.7
3.8
The watchdog timer is disabled by writing a value of 00000000 to the eight bits in the
watchdog register. Should the watchdog timer time out, a value of 00h needs to be written to
the watchdog register in order to clear the IRQ/FT pin.
The watchdog function is automatically disabled upon power-down and the watchdog
register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the
frequency test function is activated, the watchdog or alarm function prevails and the
frequency test function is denied. The WDI pin should be connected to V
Power-on reset
The M48T37Y/V continuously monitors V
point, the RST pulls low (open drain) and remains low on power-up for t
passes V
an appropriate resistor to V
page
Programmable interrupts
The M48T37Y/V provides two programmable interrupts: an alarm and a watchdog. When an
interrupt condition occurs, the M48T37Y/V sets the appropriate flag bit in the flag register
7FF0h. The interrupt enable bits (AFE and ABE) in 7FF6h and the watchdog steering
(WDS) bit in 7FF7h allow the interrupt to activate the IRQ/FT pin.
The alarm flag and the IRQ/FT output are cleared by a READ to the flags register. An
interrupt condition reset will not occur unless the addresses are stable at the flag location for
at least 15 ns while the device is in the READ mode as shown in
The IRQ/FT pin is an open drain output and requires a pull-up resistor (10 kΩ
recommended) to V
occurs or the frequency test mode is enabled.
22).
PFD
. RST is valid for all V
CC
. The pin remains in the high impedance state unless an interrupt
CC
should be chosen to control rise time (see
Doc ID 7019 Rev 9
CC
conditions. The RST pin is an open drain output and
CC
. When V
CC
falls to the power fail detect trip
Figure 7 on page
REC
SS
Clock operations
Figure 13 on
if not used.
after V
CC
14.
17/30

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