MM58174AN National Semiconductor, MM58174AN Datasheet - Page 4

• Manufacturer Part Number: MM58174AN
• Description: IC MPU CLOCK CAL 16DIP +DATA
• Manufacturer: National Semiconductor
• Type: Clock/Calendarr

Specifications of MM58174AN

• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Other names: *MM58174AN; 58174; MM58174

Circuit Description
DAYS COUNTER
There are two Days counters
a) units of days
b) tens of days
The Days counters will count up to 28 29 30 or 31 days
depending on the state of the Months counters and the
Years Status Register Days counters have parallel load and
read multiplex capabilities
MONTHS COUNTERS
There are two Months counters
a) units of months
b) tens of months
The Months counters have parallel load and read multiplex
capabilities
YEARS STATUS REGISTER
The Years Status register is a shift register of 4 bits It will be
shifted every year on December 31st The status register
must be set in accordance with Table III No readout capa-
bility is provided
CHIP SELECT (CS)
An external chip select is provided The chip enable is ac-
tive low
COUNTER AND REGISTER SELECTION
Table I shows the coding on the address lines AD0–AD3
which select the registers in the circuit to be either parallel
loaded or read on to the output bus
FIGURE 2 Crystal Oscillator
(Continued)
TL F 6681–3
4
START STOP (RESET) LATCH
A logic ‘‘1’’ on DB0 at chip address 14 (E) will start the clock
running a logic ‘‘0’’ will stop the clock This function allows
the loading of time data into the clock and its precise start-
ing The clock starts at 0 1 seconds
TEST MODE
This mode is incorporated to facilitate production testing of
the circuit In this mode the 32 768 Hz clock is fed forward
as shown in Figure 3 For normal operation the circuit must
be set to the non-test mode as part of the system initializa-
tion This is accomplished by writing a logic ‘‘0’’ to DB3 at
AD0
10 Day of Week
11 Units of Months
12 Tens of Months
13 Years
14 Stop Start
15 Interrupt
0 Test Only
1 Tenths of Secs
2 Units of Secs
3 Tens of Secs
4 Units of Mins
5 Tens of Mins
6 Units of Hours
7 Tens of Hours
8 Units of Days
9 Tens of Days
TABLE I Address Decoding for Internal Registers
Selected
Counter
FIGURE 3 Test Mode Organization
AD3 AD2 AD1 AD0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Address Bits
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Write Only
Read Only
Read Only
Read Only
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Write Only
Write Only
Read or Write
Mode
TL F 6681– 4