MCP3901T-I/SS Microchip Technology, MCP3901T-I/SS Datasheet - Page 24

• Manufacturer Part Number: MCP3901T-I/SS
• Description: IC SPI INTERFACE DUAL-CH 20-SSOP
• Manufacturer: Microchip Technology

Specifications of MCP3901T-I/SS

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): 10mW
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP3901
Each converter can be placed in Soft Reset mode
independently. The Configuration registers are not
modified by the Soft Reset mode.
A data ready pulse will not be generated by any ADC
while in Reset mode.
Reset mode also effects the modulator output block
(i.e., the MDAT pin, corresponding to the channel in
Reset).
corresponding to a zero output (a series of ‘0011’ bits
continuously repeated).
When an ADC exits ADC Reset mode, any phase delay
present, before Reset was entered, will still be present.
If one ADC was not in Reset, the ADC leaving Reset
mode will automatically resynchronize the phase delay.
The resynchronization is relative to the other ADC
channel per the Phase Delay register block and gives
DR pulses accordingly.
If an ADC is placed in Reset mode while the other is
converting, it is not shutting down the internal clock.
When going back out of Reset, it will be resynchronized
automatically with the clock that did not stop during
Reset.
If both ADCs are in Soft Reset or Shutdown modes, the
clock is no longer distributed to the digital core for low-
power operation. Once any of the ADC is back to normal
operation, the clock is automatically distributed again.
4.20
This mode is only available during a Power-on-Reset
(POR) or when the RESET pin is pulled low. The RESET
pin low state places the device in a Hard Reset mode.
In this mode, all internal registers are reset to their
default state.
The DC biases for the analog blocks are still active (i.e.,
the MCP3901 is ready to convert). However, this pin
clears all conversion data in the ADCs. In this mode,
the MDAT outputs are in high-impedance. The
comparator outputs of both ADCs are forced to their
Reset state (‘0011’). The SINC filters are all reset, as
well as their double output buffers. See serial timing for
minimum pulse low time in
Characteristics”.
During a Hard Reset, no communication with the part is
possible. The digital interface is maintained in a Reset
state.
4.21
ADC Shutdown mode is defined as a state where the
converters and their biases are off, consuming only leak-
age current. After this is removed, start-up delay time
(SINC filter settling time) will occur before outputting
meaningful codes. The start-up delay is needed to
power-up all DC biases in the channel that was in shut-
down. This delay is the same as t
coming within this delay should be discarded.
DS22192C-page 24
Hard Reset Mode (RESET = 0)
ADC Shutdown Mode
If
enabled,
it
provides
Section 1.0 “Electrical
POR
and any DR pulse
a
bitstream
Each converter can be placed in Shutdown mode,
independently. The CONFIG registers are not modified
by the Shutdown mode. This mode is only available
through programming the SHUTDOWN<1:0> bits in
the CONFIG2 register.
The output data is flushed to all zeros while in ADC
shutdown. No data ready pulses are generated by any
ADC while in ADC Shutdown mode.
ADC Shutdown mode also effects the modulator output
block (i.e., if MDAT of the channel in Shutdown mode is
enabled). This pin will provide a bitstream correspond-
ing to a zero output (series of ‘0011’ bits continuously
repeated).
When an ADC exits ADC Shutdown mode, any phase
delay present before shutdown was entered will still be
present. If one ADC was not in shutdown, the ADC
leaving Shutdown mode will automatically resynchro-
nize the phase delay relative to the other ADC channel,
per the Phase Delay register block, and give DR pulses
accordingly.
If an ADC is placed in Shutdown mode while the other
is converting, it is not shutting down the internal clock.
When going back out of shutdown, it will be
resynchronized automatically with the clock that did not
stop during Reset.
If both ADCs are in ADC Reset or ADC Shutdown
modes, there is no more distribution of the clock to the
digital core for low-power operation. Once any of the
ADC is back to normal operation, the clock is
automatically distributed again.
4.22
The lowest power consumption can be achieved when
SHUTDOWN<1:0> = 11 and VREFEXT = CLKEXT = 1.
This mode is called “Full Shutdown mode” and no ana-
log circuitry is enabled. In this mode, the POR AV
monitoring circuit is also disabled. When the clock is Idle
(CLKI = 0 or 1 continuously), no clock is propagated
throughout the chip. Both ADCs are in shutdown, the
internal voltage reference is disabled and the internal
oscillator is disabled.
The only circuit that remains active is the SPI interface,
but this circuit does not induce any static power
consumption. If SCK is Idle, the only current consump-
tion comes from the leakage currents induced by the
transistors and is less than 1 µA on each power supply.
This mode can be used to power down the chip
completely and avoid power consumption when there
is no data to convert at the analog inputs. Any SCK or
MCLK edge coming while on this mode, will induce
dynamic power consumption.
Once any of the SHUTDOWN, CLKEXT and VREFEXT
bits returns to ‘0’, the POR AV
back to operation and AV
Full Shutdown Mode
© 2010 Microchip Technology Inc.
DD
monitoring can take place.
DD
monitoring block is
DD