MCP3901T-I/SS Microchip Technology, MCP3901T-I/SS Datasheet - Page 36

• Manufacturer Part Number: MCP3901T-I/SS
• Description: IC SPI INTERFACE DUAL-CH 20-SSOP
• Manufacturer: Microchip Technology

Specifications of MCP3901T-I/SS

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): 10mW
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP3901
6.7
If the user wishes to read back either of the ADC
channels continuously, or both channels continuously,
the internal address counter of the MCP3901 can be
set to loop on specific register sets. In this case, there
is only one control byte on SDI to start the
communication. The part stays within the same loop
until CS returns high.
This internal address counter allows the following
functionality:
• Read one ADC channel’s data continuously
• Read both ADC channel’s data continuously (both
• Continuously read the entire register map
• Continuously read each separate register
• Continuously read all Configuration registers
• Write all Configuration registers in one
FIGURE 6-6:
DS22192C-page 36
SDO
SCK
ADC data can be independent or linked with
DRMODE settings)
communication (see
SDI
DR
CS
Continuous Communication,
Looping on Address Sets
These bytes are not present when WIDTH=0 (16-bit mode)
CH0 ADC
ADDR/R
Upper byte
CH0 ADC
Typical Continuous Read Communication.
Figure
Middle byte
CH0 ADC
6-6)
Lower byte
CH0 ADC
Upper byte
CH1 ADC
Middle byte
CH1 ADC
Lower byte
CH1 ADC
The STATUS/COM register contains the loop settings
for the internal address counter (READ<1:0>). The
internal address counter can either stay constant
(READ<1:0> = 00) and continuously read the same
byte, or it can auto-increment and loop through the
register groups defined below (READ<1:0> = 01),
register types (READ<1:0> = 10) or the entire register
map (READ<1:0> = 11).
Each channel is configured independently as either a
16-bit or 24-bit data word, depending on the setting of
the corresponding WIDTH bit in the CONFIG1 register.
For continuous reading, in the case of WIDTH = 0
(16-bit), the lower byte of the ADC data is not accessed
and the part jumps automatically to the following
address (the user does not have to clock out the lower
byte since it becomes undefined for WIDTH = 0).
Figure 6-6
nication with the default settings (DRMODE<1:0> = 00,
READ<1:0> = 10) for both WIDTH settings. This
configuration is typically used for power metering
applications.
Upper byte
CH0 ADC
Middle byte
CH0 ADC
represents a typical, continuous read commu-
Lower byte
CH0 ADC
Upper byte
CH1 ADC
© 2010 Microchip Technology Inc.
Middle byte
CH1 ADC
Lower byte
CH1 ADC