AD9876ABSTRL Analog Devices Inc, AD9876ABSTRL Datasheet - Page 15

• Manufacturer Part Number: AD9876ABSTRL
• Description: IC 12BIT MODEM MXFE 48-LQFP TR
• Manufacturer: Analog Devices Inc

Specifications of AD9876ABSTRL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 1
• Power (watts): 950mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 48-LQFP
• Main Category: Single Chip
• Sub-category: Converter
• Power Supply Type: Analog/Digital
• Operating Supply Voltage (typ): 3.3V
• Package Type: LQFP
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 262mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TRANSMIT PATH
The AD9876 transmit path consists of a digital interface port, a
programmable interpolation filter, and a transmit DAC. All
clock signals required by these blocks are generated from the
f
below shows the interconnection between the major functional
components of the transmit path.
DIGITAL INTERFACE PORT
The Transmit Digital Interface Port has several modes of opera-
tion. In its default configuration, the Tx Port accepts six bit
nibbles through the Tx [5:0] and Tx SYNC pins and demul-
tiplexes the data into 12-bit words before passing it to the
interpolation filter. The input data is sampled on the rising edge
of f
Additional programming options for the Tx Port allow: sampling
the input data on the falling edge of f
of f
interface can be controlled by the GAIN pin to provide direct
access to the Rx Path Gain Adjust Register. All of these modes
are fully described in the Register Programming Definitions sec-
tion of this data sheet.
The data format is twos complement, as shown below:
The data can be translated to a straight binary data format by
simply inverting the most significant bit.
The timing of the interface is fully described in the Transmit
Port Timing section of this data sheet.
PLL-A CLOCK DISTRIBUTION
Figure 1 shows the clock signals used in the transmit path. The
DAC sampling clock, f
frequency equal to L × f
generated either by the crystal oscillator when a crystal is con-
nected between the OSCIN and XTAL pins, or by the clock that
is fed into the OSCIN pin, and L is the multiplier programmed
through the serial port. L can have the values of 1, 2, 4, or 8.
REV. A
Tx QUIET
OSCIN
Tx SYNC
Tx [5:0]
011 . . 11: Maximum
000 . . 01: Midscale + 1 LSB
000 . . 00: Midscale
111 . . 11: Midscale – 1 LSB
111 . . 10: Midscale – 2 LSB
100 . . 00: Minimum
CLK-A
CLK-A
GAIN
CLK-A
signal by the PLL-A clock generator. The block diagram
, and reversing the order of the nibbles. Also, the Tx Port
.
Figure 1. Transmit Path Block Diagram
DEMUX
Tx
f
CLK-A
12
DAC
OSCIN
Kx INTERPOLATION
CLOCK GEN
, is generated by PLL-A. f
LPF/BPF
PLL-A
, where f
L
f
DAC
CLK-A
= L
OSCIN
12
, inversion or disabling
f
OSCIN
is the internal signal
TxDAC+
f
OSCIN
AD9876
DAC
has a
Tx+
Tx–
OSCIN
XTAL
–15–
The transmit path expects a new half-word of data at the rate
of f
of Tx Port is:
where K is the interpolation factor that can be programmed to be
1, 2, or 4. When the Tx multiplexer is disabled, the frequency of
the Tx Port is:
Note, this will result in a 6-bit data path.
INTERPOLATION FILTER
The interpolation filter can be programmed to run at 2× and 4×
upsampling ratios in each of three different modes. The transfer
functions of these six configurations are shown in TPCs 1–6.
The X-axis of each of these figures corresponds to the frequency
normalized to f
discrete time transfer function of the interpolation filters alone
and with the SIN(x)/x transfer function of the DAC. The
interpolation filter can also be programmed into a pass-
through mode if no interpolation filtering is desired.
The contents of the interpolation filter are not cleared by
hardware or software resets. It is recommended to “flush” the
transmit path with zeros before transmitting data.
The table below contains the following parameters as a function
of the mode that it is programmed.
Latency – The number of clock cycles from the time a digital
impulse is written to the DAC until the peak value is output at
the T+ and T– pins.
Flush – The number of clock cycles from the time a digital
impulse is written to the DAC until the output at the Tx+ and
Tx– pins settles to zero.
f
cutoff frequency of the interpolation filter as a fraction of f
the DAC sampling frequency.
f
cutoff frequency of the interpolation filter as a fraction of f
the DAC sampling frequency.
Register 7 [7:4] 0
Mode
Latency, f
Clock Cycles
Flush, f
Clock Cycles
f
f
f
f
LOWER
UPPER
LOWER,
UPPER,
LOWER,
UPPER,
CLK-A
0.1 dB
3 dB
(0.1 dB, 3 dB) – This indicates the upper 0.1 dB or 3 dB
Table I. Interpolation Filter Parameters vs. Mode
DAC
0.1 dB
3 dB
(0.1 dB, 3 dB) – This indicates the lower 0.1 dB or 3 dB
. When the Tx multiplexer is enabled, the frequency
DAC
f
CLK A
f
−
CLK A
4 × LPF 2 × LPF 4 × BPF 2 × BPF 4 × BPF 4 × BPF
86
128
0
0.102
0
0.119
DAC
=
−
0
. These transfer functions show both the
2
×
=
30
48
0
0.204
0
0.238
0
f
f
DAC
DAC
1
K
K
Adj.
86
128
0.398
0.602
0.381
0.619
0
=
=
4
2
L
×
×
L
Adj.
3
48
0.276
0.724
0.262
0.738
0
f
OSCIN
×
5
f
OSCIN
AD9876
/
K
Lower
86
148
0.148/
0.774
0.226/
0.852
0.131/
0.757
0.243/
0.869
0
/
K
8
Upper
86
142
0.274/
0.648
0.352/
0.762
0.257/
0.631
0.369/
0.743
0
DAC
DAC
C
,
,