AD9876ABSTRL Analog Devices Inc, AD9876ABSTRL Datasheet - Page 16

• Manufacturer Part Number: AD9876ABSTRL
• Description: IC 12BIT MODEM MXFE 48-LQFP TR
• Manufacturer: Analog Devices Inc

Specifications of AD9876ABSTRL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 1
• Power (watts): 950mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 48-LQFP
• Main Category: Single Chip
• Sub-category: Converter
• Power Supply Type: Analog/Digital
• Operating Supply Voltage (typ): 3.3V
• Package Type: LQFP
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 262mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

AD9876
D/A CONVERTER
The AD9876 DAC provides differential output current on the
Tx+ and Tx– pins. The value of the output currents are comple-
mentary, meaning that they will always sum to I
current of the DAC. For example, when the current from Tx+ is
at full-scale, the current from Tx– is zero. The two currents will
typically drive a resistive load that will convert the output
currents to a voltage. The Tx+ and Tx– output currents are
inherently ground seeking and should each be connected to
matching resistors, R
The full-scale output current of the DAC is set by the value of
the resistor placed from the FSADJ pin to AGND. The relation-
ship between the resistor, R
is governed by the following equation:
The full-scale current can be set from 2 to 20 mA. Generally,
there is a trade-off between DAC performance and power con-
sumption. The best DAC performance will be realized at an I
of 20 mA. However, the value of I
current consumption of the device.
The single-ended voltage output appearing at the Tx+ and Tx–
nodes are:
Note that the full-scale voltage of V
exceed the maximum output compliance range of 1.5 V to pre-
vent signal compression. To maintain optimum distortion and
linearity performance, the maximum voltages at V
should not exceed 0.5 V.
The single-ended full-scale voltage at either output node will be:
The differential voltage, V
For optimum performance, a differential output interface is rec-
ommended since any common-mode noise or distortion can be
suppressed.
It should be noted that the differential output impedance of the
DAC is 2 × R
resistors will load down the output voltage accordingly.
RECEIVE PATH DESCRIPTION
The receive path consists of a two-stage PGA, a continuous time,
4-pole LPF, an ADC, a digital HPF, and a digital data multiplexer.
Also working in conjunction with the receive path is an offset
correction circuit and a digital phase-lock loop. Each of these
blocks will be discussed in detail in the following sections.
PROGRAMMABLE GAIN AMPLIFIER
The PGA has a programmable gain range from –6 dB to +36 dB
if the narrower (approximately 12 MHz) LPF bandwidth is
L
and any load connected across the two output
V
DIFF
V
L
, that are tied directly to AGND.
DIFF
V
V
V
I
FS
Tx
Tx
=
FS
DIFF
+
−
(
_
T
SET
= 39 4 .
FS
=
=
=
Tx
, appearing across V
and
, and the full-scale output current
I
I
I
+
=
Tx
Tx
FS
−
I
+
−
FS
T
FS
Tx+
R
×
×
×
Tx
SET
adds directly to the overall
R
R
R
×
−
and V
L
L
L
)
R
×
L
R
Tx–
L
FS
should not
Tx+
, the full-scale
Tx+
and V
and V
Tx–
Tx–
FS
is:
–16–
selected, or if the LPF is bypassed. If the wider (approximately
26 MHz) LPF bandwidth is selected, the gain range is –6 dB to
+30 dB. The PGA is comprised of two sections, a continuous
time PGA (CPGA) and a switched capacitor PGA (SPGA). The
CPGA has possible gain settings of 0, 6, 12, 18, 24, and 30. The
SPGA has possible gain settings of –6, –4, –2, 0, +2, +4, and +6
dB. Table V shows how the gain is distributed for each pro-
grammed gain setting.
The CPGA input appears at the device Rx+ and Rx– input pins.
The input impedance of this stage is nominally 270
tial and is not gain dependent. It is best to ac-couple the input
signal to this stage and let the inputs self bias. This will lower
the offset voltage of the input signal, which is important at higher
gains, since any offset will lower the output compliance range of
the CPGA output. When the inputs are driven by direct coupling,
the dc level should be AVDD/2. However, this could lead to
larger dc offsets and consequently reduce the dynamic range of the
Rx path.
LOW-PASS FILTER
The low-pass filter (LPF) is a programmable, multistage, fourth
order filter comprised of two real poles and a complex pole pair.
The first real pole is implemented within the CPGA. The second
filter stage implements a complex pair of poles. The last real
pole is implemented in a buffer stage that drives the SPGA.
There are two pass-band settings for the LPF. Within each pass
band the filters are tunable over about a ± 30% frequency range.
The formula for the cutoff frequency is:
where Target is the decimal value programmed as the tuning
target in Register 5.
This filter may also be bypassed by setting Bit 0 of Register 4.
In this case, the bandwidth of the Rx path will decrease with
increasing gain and will be approximately 50 MHz at the highest
gain settings.
ADC
The AD9876’s analog-to-digital converter implements a pipe-
lined multistage architecture to achieve high sample rates while
consuming low power. The ADC distributes the conversion over
several smaller A/D subblocks, refining the conversion with
progressively higher accuracy as it passes the results from stage
to stage. As a consequence of the distributed conversion, ADCs
require a small fraction of the 2
tional n-bit flash-type A/D. A sample-and-hold function within
each of the stages permits the first stage to operate on a new
input sample while the remaining stages operate on preceding
samples. Each stage of the pipeline, excluding the last, consists
of a low resolution flash A/D connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). The residue
amplifier amplifies the difference between the reconstructed
DAC output and the flash input for the next stage in the pipe-
line. One bit of redundancy is used in each one of the stages to
facilitate digital correction of flash errors. The last stage simply
consists of a flash A/D.
f
CUTOFF HIGH
f
CUTOFF LOW
=
=
f
f
ADC
ADC
N
×
×
comparators used in a tradi-
158 64
64 64
(
(
+
+
Target
Target
)
)
differen-
REV. A