AD7699BCPZ Analog Devices Inc, AD7699BCPZ Datasheet - Page 24

• Manufacturer Part Number: AD7699BCPZ
• Description: IC ADC 8CH 16BIT 500KSPS 20LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD7699BCPZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Number Of Converters: 1
• Power Dissipation (max): 32mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN, CSP Exposed Pad
• Resolution (bits): 16bit
• Sampling Rate: 500kSPS
• Input Channel Type: Pseudo Differential, Single Ended
• Supply Voltage Range - Analog: 4.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7699
GENERAL TIMING WITH A BUSY INDICATOR
Figure 38 details the timing for all three modes: reading/writing
during conversion, after conversion, and spanning conversion.
Note that the gating item for both CFG and data readback is at
the end of conversion (EOC). As detailed previously, the data
access should occur up to safe data reading/writing time, t
If the full CFG word is not written to prior to EOC, it is
discarded and the current configuration remains.
At the EOC, if CNV is low, the busy indicator is enabled. In
addition, to generate the busy indicator properly, the host must
assert a minimum of 17 SCK falling edges to return SDO to
high impedance because the last bit of data on SDO remains
active. Unlike the case detailed in the General Timing Without
a Busy Indicator section, if the conversion result is not read out
PHASE
SDO
SDO
SDO
CNV
SCK
CNV
SCK
CNV
SCK
NOTES
1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.
DIN
DIN
DIN
A TOTAL OF 17 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK
IS ENABLED, A TOTAL OF 31 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.
POWER
UP
CONVERSION (n – 2)
1
t
DATA
t
CONV
XXX
XXX
17/31
t
CYC
ACQUISITION
1
1
DATA (n – 2)
START OF CONVERSION
(n –1)
CFG (n)
Figure 38. General Interface Timing for the AD7699 With a Busy Indicator
DATA
(n – 2)
17/31
CFG (n)
CONVERSION (n – 1)
1
(n – 2)
DATA
CFG (n)
17/31
END OF CONVERSION (EOC)
(n – 2)
DATA
17/31
DATA
Rev. 0 | Page 24 of 28
.
ACQUISITION
1
1
CFG (n + 1)
DATA
(n – 1)
(n)
(n – 1)
DATA
17/31
CFG (n + 1)
fully prior to EOC, the last bit clocked out remains. If this bit is
low, the busy signal indicator cannot be generated because the
digital output requires a high impedance, or a bit remaining high,
to low transition for the interrupt input of the host. A good
example of this occurs when an SPI host sends 16 SCKs because
these are usually limited to 8-bit or 16-bit bursts, thus the LSB
remains. Because the transition noise of the AD7699 is 4 LSBs
peak to peak (or greater), the LSB is low 50% of the time. For
this interface, the SPI host needs to burst 24 SCKs, or a QSPI
interface can be used and programmed for 17 SCKs.
The SCK can idle high or low depending on the CPOL and
CPHA settings if SPI is used. A simple solution is to use CPOL
= CPHA = 1 (not shown) with SCK idling high.
CONVERSION (n)
1
(n – 1)
CFG (n + 1)
DATA
17/31
(n – 1)
DATA
17/31
EOC
ACQUISITION
1
CFG (n + 2)
1
(n + 1)
DATA (n)
DATA (n)
17/31
CFG (n + 2)
CONVERSION (n + 1)
1
DATA (n)
CFG (n + 2)
17/31
DATA (n)
17/31
EOC
ACQUISITION
1
1
CFG (n + 3)
CFG (n + 3)
DATA (n + 1)
DATA (n + 1)
(n + 2)