AD9246BCPZ-125 Analog Devices Inc, AD9246BCPZ-125 Datasheet - Page 7

• Manufacturer Part Number: AD9246BCPZ-125
• Description: IC ADC 14BIT 125MSPS 48-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9246BCPZ-125

• Data Interface: Serial, SPI™
• Design Resources: Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051)
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Number Of Converters: 3
• Power Dissipation (max): 425mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 14bit
• Sampling Rate: 125MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9246-125EBZ - BOARD EVAL FOR 125MSPS AD9246AD9246-105EBZ - BOARD EVAL FOR 105MSPS AD9246
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
OUT-OF-RANGE RECOVERY TIME
SERIAL PORT INTERFACE
1
2
3
4
TIMING DIAGRAM
See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB.
See Figure 57 and the Serial Port Interface (SPI) section.
Conversion Rate, DCS Enabled
Conversion Rate, DCS Disabled
CLK Period
CLK Pulse Width High, DCS Enabled
CLK Pulse Width High, DCS Disabled
Data Propagation Delay (t
DCO Propagation Delay (t
Setup Time (t
Hold Time (t
Pipeline Delay (Latency)
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Wake-Up Time
SCLK Period (t
SCLK Pulse Width High Time (t
SCLK Pulse Width Low Time (t
SDIO to SCLK Setup Time (t
SDIO to SCLK Hold Time (t
CSB to SCLK Setup Time (t
CSB to SCLK Hold Time (t
1
H
)
S
)
CLK
3
)
A
)
4
DATA
CLK+
CLK–
DCO
H
DCO
PD
S
)
DH
)
DS
)
)
2
)
)
J
LO
)
HI
)
)
N – 13
N
t
S
t
t
A
PD
N – 12
N + 1
t
CLK
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
t
H
N – 11
N + 2
Min
20
10
12.5
3.75
5.63
3.1
4.9
5.9
40
16
16
5
2
5
2
Figure 2. Timing Diagram
AD9246BCPZ-80
N – 10
N + 3
Rev. A | Page 7 of 44
Typ
6.25
6.25
3.9
4.4
5.7
6.8
12
0.8
0.1
350
2
t
DCO
N – 9
N + 4
Max
80
80
8.75
6.88
4.8
N – 8
N + 5
Min
20
10
9.5
2.85
4.28
3.1
3.4
4.4
40
16
16
5
2
5
2
t
AD9246BCPZ-105
CLK
N + 6
N – 7
Typ
4.75
4.75
3.9
4.4
4.3
5.3
12
0.8
0.1
350
2
N + 7
N – 6
Max
105
105
6.65
5.23
4.8
N + 8
N – 5
Min
20
10
8
2.4
3.6
3.1
2.6
3.7
40
16
16
5
2
5
2
N – 4
AD9246BCPZ-125
Typ
4
4
3.9
4.4
3.5
4.5
12
0.8
0.1
350
3
Max
125
125
5.6
4.4
4.8
AD9246
ns
ns
ps rms
Cycles
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
cycles
ns
μs
ns
ns
ns
ns
ns
ns
ns