ADC10065CIMT/NOPB National Semiconductor, ADC10065CIMT/NOPB Datasheet

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ADC10065CIMT/NOPB

Manufacturer Part Number
ADC10065CIMT/NOPB
Description
IC ADC 10BIT 65MSPS 3V 28-TSSOP
Manufacturer
National Semiconductor
Series
PowerWise®r
Datasheet

Specifications of ADC10065CIMT/NOPB

Number Of Bits
10
Sampling Rate (per Second)
65M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
68.4mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP (0.173", 4.40mm Width)
Number Of Elements
1
Resolution
10Bit
Architecture
Pipelined
Sample Rate
65MSPS
Input Polarity
Bipolar
Input Type
Voltage
Rated Input Volt
±0.5/±0.75/±1V
Differential Input
Yes
Power Supply Requirement
Single
Single Supply Voltage (typ)
3V
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
3.6V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Power Dissipation
68.4mW
Differential Linearity Error
±0.9LSB
Integral Nonlinearity Error
-1LSB/1.1LSB
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Package Type
TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*ADC10065CIMT
*ADC10065CIMT/NOPB
ADC10065CIMT
© 2008 National Semiconductor Corporation
ADC10065
10-Bit 65 MSPS 3V A/D Converter
General Description
The ADC10065 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 10-bit
digital words at 65 Megasamples per second (MSPS). This
converter uses a differential, pipeline architecture with digital
error correction and an on-chip sample-and-hold circuit to
provide a complete conversion solution, and to minimize pow-
er consumption, while providing excellent dynamic perfor-
mance. A unique sample-and-hold stage yields a full-power
bandwidth of 400 MHz. Operating on a single 3.0V power
supply, this device consumes just 68.4 mW at 65 MSPS, in-
cluding the reference current. The Standby feature reduces
power consumption to just 14 .1 mW.
The differential inputs provide a full scale selectable input
swing of 2.0 V
single-ended input. Full use of the differential input is recom-
mended for optimum performance. An internal +1.2V preci-
sion bandgap reference is used to set the ADC full-scale
range, and also allows the user to supply a buffered refer-
enced voltage for those applications requiring increased ac-
curacy. The output data format is user choice of offset binary
or two’s complement.
This device is available in the 28-lead TSSOP package and
will operate over the industrial temperature range of −40°C to
+85°C.
Connection Diagram
P-P
, 1.5 V
P-P
, 1.0 V
P-P
, with the possibility of a
200779
Features
Key Specifications
Applications
Single +3.0V operation
Selectable 2 V
400 MHz −3 dB input bandwidth
Low power consumption
Standby mode
On-chip reference and sample-and-hold amplifier
Offset binary or two’s complement data format
Separate adjustable output driver supply to accommodate
2.5V and 3.3V logic families
28-pin TSSOP package
Resolution
Conversion Rate
Full Power Bandwidth
DNL
SNR (f
SFDR (f
Power Consumption, 65 MHz
Ultrasound and Imaging
Instrumentation
Cellular Base Stations/Communications Receivers
Sonar/Radar
xDSL
Wireless Local Loops
Data Acquisition Systems
DSP Front Ends
IN
IN
= 11 MHz)
= 11 MHz)
P-P
20077901
, 1.5 V
P-P
, or 1 V
P-P
full-scale input
February 1, 2008
±0.3 LSB (typ)
www.national.com
59.6 dB (typ)
−80 dB (typ)
65 MSPS
400 MHz
68.4 mW
10 Bits

Related parts for ADC10065CIMT/NOPB

ADC10065CIMT/NOPB Summary of contents

Page 1

... The output data format is user choice of offset binary or two’s complement. This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C. Connection Diagram © 2008 National Semiconductor Corporation Features ■ Single +3.0V operation ■ Selectable 2 V ■ ...

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Ordering Information Industrial (−40°C Use ADC10080EVAL Block Diagram www.national.com ≤ ≤ T +85°C) A ADC10065CIMT ADC10065CIMTX 28 Pin TSSOP Tape & Reel 2 NS Package 28 Pin TSSOP Evaluation Board 20077902 ...

Page 3

Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I − REF 7 V REFT V 4 COM V 8 REFB DIGITAL I/O 1 CLK STBY IRS (Input ...

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Pin No. Symbol 16–20, 23– D0–D9 27 ANALOG POWER DDA V 3, 11, 14 SSA DIGITAL POWER V 22 DDIO V 21 SSIO www.national.com Equivalent Circuit Digital output data the LSB and D9 is ...

Page 5

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications DDA DDIO Voltage on Any Pin to GND Input Current on Any Pin Package Input Current (Note 3) Package Dissipation 25°C ESD Susceptibility Human Body Model (Note 5) Machine Model (Note 5) Soldering Temperature Infrared, 10 sec ...

Page 6

DC and Logic Electrical Characteristics for 0V +3.0V, V SSA SSIO DDA Cycle pF/pin. Boldface limits apply for T L Symbol CLK, DF, STBY, SENSE Logical “1” Input Voltage Logical “0” ...

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AC Electrical Characteristics Unless otherwise specified, the following specifications apply for V STBY = 0V 1.20V (External), f REF T : all other limits T = 25°C MAX A Symbol Parameter CLK, DF, STBY, SENSE f 1 Maximum ...

Page 8

Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...

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Timing Diagram Transfer Characteristics FIGURE 2. Input vs. Output Transfer Characteristic FIGURE 1. Clock and Data Timing Diagram 9 20077909 20077910 www.national.com ...

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Typical Performance Characteristics 0V +3.0V, V SSA SSIO DDA 50% Duty Cycle. DNL DNL vs. Clock Duty Cycle (DC input) www.national.com Unless otherwise specified, the following specifications apply: = +2.5V ...

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INL 20077914 INL vs. Clock Duty Cycle 20077918 SNR vs. V DDA 20077920 INL vs. f CLK SNR vs. V DDIO SNR vs. f CLK 11 20077917 20077919 20077921 www.national.com ...

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INL vs. Temperature SNR vs. Temperature THD vs. V www.national.com 20077922 20077924 DDIO 20077926 12 SNR vs. Clock Duty Cycle 20077923 THD vs. V DDA 20077925 THD vs. f CLK 20077927 ...

Page 13

SNR vs. IRS 20077928 SINAD vs. V DDA 20077930 THD vs. Clock Duty Cycle 20077932 THD vs. IRS SINAD vs. V DDIO SINAD vs. Clock Duty Cycle 13 20077929 20077931 20077933 www.national.com ...

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THD vs. Temperature SINAD vs. f SINAD vs. IRS www.national.com 20077934 CLK 20077936 20077938 14 SINAD vs. Temperature 20077935 SFDR vs. V DDIO 20077937 SFDR vs. f CLK 20077939 ...

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SFDR vs. V DDA 20077940 SFDR vs. Clock Duty Cycle 20077942 SFDR vs. Temperature 20077944 SFDR vs. IRS Spectral Response @ 11 MHz Input Spectral Response @ 32 MHz Input 15 20077941 20077943 20077945 www.national.com ...

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Power Consumption vs. f www.national.com CLK 20077946 16 ...

Page 17

Functional Description The ADC10065 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 10 bits. In dif- ferential mode, each analog input signal should have a peak- to-peak ...

Page 18

TABLE 1. IRS Pin Functions IRS Pin Full-Scale Input V DDA V SSA Floating 1.8 OUTPUT PINS The ADC10065 has 10 TTL/CMOS compatible Data Output pins. The offset binary data is present at these outputs while the DF and STBY ...

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FIGURE 6. A Simple Application Using a Single Ended Driving Source 19 20077950 www.national.com ...

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Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 28-Lead TSSOP Package Ordering Number ADC10065CIMT NS Package Number MTC28 20 ...

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Notes 21 www.national.com ...

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