AD7859LASZ Analog Devices Inc, AD7859LASZ Datasheet
AD7859LASZ
Specifications of AD7859LASZ
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AD7859LASZ Summary of contents
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FEATURES Specified for 5 AD7859–200 kSPS; AD7859L–100 kSPS System and Self-Calibration Low Power Normal Operation AD7859 AD7859L: 5 Using ...
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AD7859/AD7859L–SPECIFICATIONS External Reference MHz (for L Version: 1.8 MHz ( +70 C) and 1 MHz (– +85 C)); f CLKIN (AD7859L); SLEEP = Logic High MIN Parameter ...
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Parameter A Version CONVERSION RATE Conversion Time 4.5 (10) Track/Hold Acquisition Time 0.5 (1) POWER REQUIREMENTS AV DV +3.0/+5.5 DD Normal Mode 5.5 (1.95) 5.5 (1.95) 6 Sleep Mode With External Clock On 10 400 With ...
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AD7859/AD7859L 1 TIMING SPECIFICATIONS Limit MIN (A, B Versions) Parameter 500 500 CLKIN 4 4 1.8 1 100 100 4.5 4.5 CONVERT ...
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TO OUTPUT PIN 50pF 200µA Figure 1. Load Circuit for Digital Output Timing Specifications ORDERING GUIDE Linearity Error 1 Model (LSB) AD7859AP 1 AD7859AS 1 AD7859BS 1/2 3 AD7859LAS 1 4 EVAL-AD7859CB 5 EVAL-CONTROL BOARD NOTES 1 Linearity error ...
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AD7859/AD7859L TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end- points of the transfer function are zero scale, a point 1/2 LSB below the first code ...
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Mnemonic Description CONVST Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion. When this input is not used, it should be tied Read Input. ...
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AD7859/AD7859L AD7859/AD7859L ON-CHIP REGISTERS The AD7859/AD7859L powers up with a set of default conditions. The only writing that is required is to select the channel configu- ration. Without performing any other write operations, the AD7859/AD7859L still retains the flexibility for ...
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CONTROL REGISTER The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function ...
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AD7859/AD7859L Table IIIa. Channel Selection for AD7859/AD7859L Differential Sampling (SGL/DIFF = 0) AMODE CHSLT AIN(+)*AIN(–)* AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 ...
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STATUS REGISTER The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by first writing to the control register and putting two 1s ...
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AD7859/AD7859L CALIBRATION REGISTERS The AD7859/AD7859L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read from all 10 calibration registers. In self and system calibration, the ...
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START WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 CAL REGISTER POINTER IS AUTOMATICALLY RESET READ CAL REGISTER CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED LAST REGISTER ...
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AD7859/AD7859L CIRCUIT INFORMATION The AD7859/AD7859L is a fast, 8-channel, 12-bit, single sup- ply A/D converter. The part requires an external 4 MHz/1.8 MHz master clock (CLKIN), two C REF signal to start conversion and power supply decoupling capaci- tors. The ...
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ANALOG INPUT The equivalent analog input circuit is shown in Figure 9. AIN(+) is the channel connected to the positive input of the track/hold circuitry and AIN(–) is the channel connected to the negative input. Please refer to Table IIIa ...
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AD7859/AD7859L +3V TO +5V 10µF 10k 10k (– /2) REF REF IC1 10k V /2 REF AD820 V– AD820-3V 10k Figure 11. Analog Input Buffering Input Ranges The analog input range for the ...
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REFERENCE SECTION For specified performance recommended that when using an external reference, this reference should be between 2.3 V and the analog supply AV . The connections for the reference DD pins are shown below. If the internal ...
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AD7859/AD7859L – 3.3V/5. 100mV pk-pk SINEWAVE –80 –82 –84 –86 –88 – INPUT FREQUENCY – kHz Figure 20. PSRR vs. Frequency POWER-DOWN OPTIONS The AD7859/AD7859L provides flexible ...
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START CONVERSION ON RISING EDGE POWER UP ON FALLING EDGE 5µs 4.6µs CONVST t CONVERT BUSY POWER-UP NORMAL TIME OPERATION POWER-DOWN Figure 21. Using the CONVST Pin to Power Up the AD7859 for a Conversion Using The Internal (On-Chip) Reference ...
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AD7859/AD7859L AD7859 FULL POWER-DOWN CLKIN = 4MHz DD 1 ON-CHIP REFERENCE 0.1 0. THROUGHPUT RATE – kSPS Figure 24. Power vs. Throughput AD7859 AD7859L FULL POWER-DOWN CLKIN = 1.8MHz DD ...
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CALIBRATION SECTION Calibration Overview The automatic calibration that is performed on power-up ensures that the calibration options covered in this section are not required in a significant number of applications. A calibra- tion does not have to be initiated unless ...
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AD7859/AD7859L Self-Calibration Timing Figure 29 shows the timing for a software full self-calibration. Here the BUSY line stays high for the full length of the self- calibration. A self-calibration is initiated by writing to the control register and setting the ...
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System Gain and Offset Interaction The architecture of the AD7859/AD7859L leads to an interac- tion between the system offset and gain errors when a system calibration is performed. Therefore recommended to per- form the cycle of a system ...
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AD7859/AD7859L CONVST BUSY DB0 – DB15 INTERNAL DATA LATCH * W/B PIN LOGIC HIGH Figure 35. Read and Write Cycle Timing Diagram for 16-Bit Transfers PARALLEL INTERFACE The AD7859 provides a flexible, high speed, parallel interface. This ...
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HBEN CS WR DB0 – DB7 * W/B PIN LOGIC LOW Figure 37. Write Cycle Timing for Byte Mode Operation Writing With W logic high, a single write operation transfers the full data word to the AD7859. The ...
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AD7859/AD7859L The parallel interface on the AD7859/AD7859L is fast enough to interface to the TMS32020 with no extra wait states. If high speed glue logic such as 74AS devices are used to drive the WR and RD lines when interfacing ...
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DGND connection, then the ground planes should be con- nected at the AGND and DGND pins of the AD7859/ AD7859L. If the AD7859/AD7859L system where mul- tiple devices require AGND to DGND connections, the con- nection should ...
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