LTC1864LACMS8#TR Linear Technology, LTC1864LACMS8#TR Datasheet - Page 10

• Manufacturer Part Number: LTC1864LACMS8#TR
• Description: IC ADC 16-BIT 1CH 150KSPS 8-MSOP
• Manufacturer: Linear Technology

Specifications of LTC1864LACMS8#TR

• Number Of Bits: 16
• Sampling Rate (per Second): 150k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 400mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1864L/LTC1865L
APPLICATIO S I FOR ATIO
LTC1865L OPERATION
Operating Sequence
The LTC1865L conversion cycle begins with the rising
edge of CONV. After a period equal to t
sion is finished. If CONV is left high after this time, the
LTC1865L goes into sleep mode drawing only leakage
current. The LTC1865L’s 2-bit data word is clocked into
the SDI input on the rising edge of SCK after CONV goes
low. Additional inputs on the SDI pin are then ignored until
the next CONV cycle. The shift clock (SCK) synchronizes
the data transfer with each bit being transmitted on the
falling SCK edge and captured on the rising SCK edge in
both transmitting and receiving systems. The data is
transmitted and received simultaneously (full duplex).
After completing the data transfer, if further SCK clocks
are applied with CONV low, SDO will output zeros indefi-
nitely. See Figure 4.
Analog Inputs
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the
“+” and “–” signs in the selected row of Table 1. In
10
CONV
SDO
SCK
SDI
U
t
CONV
U
DON'T CARE
DON’T CARE
Hi-Z
W
CONV
Figure 4. LTC1865L Operating Sequence
, the conver-
SLEEP MODE
U
single-ended mode, all input channels are measured with
respect to GND. A zero code will occur when the “+” input
minus the “–” input equals zero. Full scale occurs when
the “+” input minus the “–” input equals V
1LSB. See Figure 5. Both the “+” and “–” inputs are
sampled at the same time so common mode noise is
rejected. The input span in the SO-8 package is fixed at
V
grounded, a rail-to-rail input span will result on the “+”
input.
Reference Input
The reference input of the LTC1865L SO-8 package is
internally tied to V
therefore equal to V
of the LTC1865L MSOP package defines the span of the
A/D converter. The LTC1865L MSOP package can operate
with reference voltages from 1V to V
REF
SINGLE-ENDED
DIFFERENTIAL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
S/D O/S
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
B15 B14
MUX MODE
MUX MODE
1
= V
2
B13
3
CC
B12
. If the “–” input in differential mode is
4
B11
Table 1. Multiplexer Channel Selection
5
SGL/DIFF
B10
6
MUX ADDRESS
CC
1
1
0
0
CC
B9
7
. The span of the A/D converter is
. The voltage on the reference input
B8
t
8
DON’T CARE
SMPL
B7
ODD/SIGN
9
B6
10
0
1
0
1
B5
11
12
B4
B3
13
CC
CHANNEL #
0
+
+
–
14
B2
.
B1
15
16
B0*
sn18645L 18645Lfs
1
+
–
+
1864 F04
REF
Hi-Z
GND
minus
–
–
1864 TBL1