LTC1418IG Linear Technology, LTC1418IG Datasheet

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... DC to 10MHz. A separate convert start input and a data ready signal (BUSY) allow easy control of conversion start and data transfer. , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation ...

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... INFORMATION ORDER PART TOP VIEW NUMBER LTC1418ACG BUSY 26 LTC1418ACN 25 CS LTC1418AIG 24 CONVST LTC1418AIN 23 RD LTC1418CG 22 SHDN LTC1418CN 21 SER/PAR LTC1418IG 20 D0 (EXT/INT) LTC1418IN OUT 18 D2 (CLKOUT (SCLK (EXTCLKIN PACKAGE 28-LEAD NARROW PDIP = 110 ( 110 C, = 100 C/ W (N) JA LTC1418 LTC1418A TYP MAX MIN ...

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ACCURACY SYMBOL PARAMETER S/( Signal-to-Noise Plus Distortion Ratio THD Total Harmonic Distortion SFDR Spurious Free Dynamic Range IMD Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth TER AL REFERE ...

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LTC1418 CHARACTERISTICS SYMBOL PARAMETER f Maximum Sampling Frequency SAMPLE(MAX) t Conversion Time CONV t Acquisition Time ACQ Acquisition Plus Conversion Time ACQ CONV Setup Time ...

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W U TYPICAL PERFORMANCE CHARACTERISTICS Typical INL Curve 1.0 0.5 0 –0.5 –1.0 0 4096 8192 12288 16384 OUTPUT CODE 1418 TA02 Signal-to-Noise Ratio vs Input Frequency 10k 100k ...

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LTC1418 W U TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Feedthrough vs Ripple Frequency 0 –20 –40 – –80 DD DGND –100 –120 1k 10k 100k 1M 10M FREQUENCY (Hz) 1418 G08 V Supply Current vs DD Temperature (Unipolar ...

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PIN FUNCTIONS + A (Pin 1): Positive Analog Input. IN – A (Pin 2): Negative Analog Input (Pin 3): 2.50V Reference Output. Bypass to AGND REF with 1 F. REFCOMP (Pin 4): 4.096V Reference Bypass ...

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LTC1418 U U FUNCTIONAL BLOCK DIAGRA + A IN – 2.5V V 2.5V REF REF REF AMP 4.096V REFCOMP AGND INTERNAL MUX DGND CLOCK D4 (EXTCLKIN) D0 (EXT/INT) NOTE: PIN NAMES IN PARENTHESES REFER TO SERIAL MODE ...

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U U APPLICATIONS INFORMATION + Referring to Figure 1, the A and A IN nected to the sample-and-hold capacitors (C ing the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum ...

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LTC1418 U U APPLICATIONS INFORMATION 10k 100k INPUT FREQUENCY (Hz) Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency Total Harmonic Distortion Total harmonic ...

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... DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1418. More detailed information is available in the Linear Technology Databooks and on the LinearView ® LT 1354: 12MHz, 400V Amp ...

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LTC1418 U U APPLICATIONS INFORMATION amplifier. 2.2V to 15V supplies. Good AC performance, input noise voltage = 12nV/ Hz (typ). LT1630/LT1631: 30MHz, 10V/ s, Dual/Quad Rail-to-Rail Input and Output Precision Op Amps. 3.5mA supply current per amplifier. 2.7V to 15V ...

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U U APPLICATIONS INFORMATION UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT Figure 9a shows the ideal input/output characteristics for the LTC1418. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, … FS – 1.5LSB). The output ...

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LTC1418 U U APPLICATIONS INFORMATION error adjustment is achieved by adjusting the offset – applied to the A input. For zero offset error apply IN + – 125 V (i.e., – 0.5LSB and adjust the offset IN – ...

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U U APPLICATIONS INFORMATION W U LTC1418 15 ...

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LTC1418 U U APPLICATIONS INFORMATION Figure 12b. Suggested Evaluation Circuit Board— Component Side Top Silkscreen Figure 12c. Suggested Evaluation Circuit Board—Top Layer 1418 F12b 1418 F12c ...

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U U APPLICATIONS INFORMATION Figure 12d. Suggested Evaluation Circuit Board—Solder Side Layout Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be ...

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LTC1418 U U APPLICATIONS INFORMATION mode is much slower since the reference circuit must power up and settle to 0.005% for full 14-bit accuracy. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP ...

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U U APPLICATIONS INFORMATION (SAMPLE N) CONVST t 6 BUSY DATA (N – 1) DATA DB13 TO DB0 Figure 15. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ...

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LTC1418 U U APPLICATIONS INFORMATION (SAMPLE CONVST t 6 BUSY t 10 DATA (SAMPLE CONVST t 6 BUSY DATA outputs; BUSY goes high releasing the processor and the ...

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U U APPLICATIONS INFORMATION CLOCK DATA IN 14 SAR 16 CONVERSION CLOCK CYCLES EOC Figure 20. Functional Block Diagram for Serial Mode (SER/PAR = High) asynchronous clocks. To maintain accuracy the external conversion clock frequency must be between 30kHz and ...

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LTC1418 U U APPLICATIONS INFORMATION two zeros. The MSB (D13) will be valid on the first rising and the first falling edge of the SCLK. D12 will be valid on the second rising and the second falling edge as will ...

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U U APPLICATIONS INFORMATION serial port after transferring the serial output data by tying it to the RD pin. Figures show several serial modes of operation, demonstrating the flexibility of the LTC1418 serial port. Serial Data Output ...

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LTC1418 U U APPLICATIONS INFORMATION clock to EXTCLKIN. The same clock is also applied to SCLK to provide a data shift clock. To maintain accuracy the conversion clock frequency must be between 30kHz and 4.5MHz not recommended to ...

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U U APPLICATIONS INFORMATION also allows operation when the SCLK frequency is very low (less than 30kHz). To select the internal conversion clock tie EXT/INT low. The external SCLK is applied to SCLK. RD can be used to gate the ...

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LTC1418 U U APPLICATIONS INFORMATION allows the user to synchronize the A/D conversion to an external clock either to have precise control of the internal bit test timing or to provide a precise conversion time Figure 24, this ...

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... MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ...

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... Input, SINAD = 90dB, THD = 100dB Low Power, 10V Inputs, Parallel/Byte Interface 1LSB Max INL/DNL, 1nV • sec Glitch, DAC8043 Upgrade 1LSB Max INL/DNL, DAC8143/AD7543 Upgrade 0.05% Max, 5ppm/ C Max 1N5817* CAN BECOME SS 1418f LT/TP 0798 4K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1998 ...