LTC1603CG Linear Technology, LTC1603CG Datasheet - Page 9

• Manufacturer Part Number: LTC1603CG
• Description: IC ADC W/SHUTDOWN 16BIT 36-SSOP
• Manufacturer: Linear Technology

Specifications of LTC1603CG

• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 350mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
CONVST Pulse Returns High Early in the Conversion or After
the End of Conversion
4
3
2
1
0
0
Figure 2b. SHDN to CONVST Wake-Up Timing
Figure 2a. Nap Mode to Sleep Mode Timing
500
CONVST
Figure 3. CS to CONVST Setup Timing
CONVST
SHDN
SHDN
CS
1000
RD
CS
t
CONV
U
1500
CONVST LOW TIME, t
INFORMATION
t
t
1
U
3
t
t
2
4
2000
2500
W
5
(ns)
3000
1603 F02a
1603 F03
1603 F02b
3500
t
ACQ
U
1603 F04
4000
currents are shut down and only leakage current remains
(about 1 A). Wake-up time from Sleep mode is much
slower since the reference circuit must power up and
settle. Sleep mode wake-up time is dependent on the value
of the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 160ms with the recommended 47 F
capacitor.
Shutdown is controlled by Pin 33 (SHDN). The ADC is in
shutdown when SHDN is low. The shutdown mode is
selected with Pin 32 (CS). When SHDN is low, CS low
selects nap and CS high selects sleep.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A falling edge
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY is
low during a conversion.
We recommend using a narrow logic low or narrow logic
high CONVST pulse to start a conversion as shown in
Figures 5 and 6. A narrow low or high CONVST pulse
prevents the rising edge of the CONVST pulse from upset-
ting the critical bit decisions during the conversion time.
Figure 4 shows the change of the differential nonlinearity
error versus the low time of the CONVST pulse. As shown,
if CONVST returns high early in the conversion (e.g.,
CONVST low time <500ns), accuracy is unaffected. Simi-
larly, if CONVST returns high after the conversion is over
(e.g., CONVST low time >t
For best results, keep t
t
Figures 5 through 9 show several different modes of
operation. In modes 1a and 1b (Figures 5 and 6), CS and
RD are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 7) CS is tied low. The falling edge of
CONVST signal starts the conversion. Data outputs are in
CONV
.
5
less than 500ns or greater than
CONV
), accuracy is unaffected.
LTC1603
9
1603f