ADC1001CCJ-1 National Semiconductor, ADC1001CCJ-1 Datasheet - Page 6

• Manufacturer Part Number: ADC1001CCJ-1
• Description: IC ADC 10BIT MPU COMPAT 20-CDIP
• Manufacturer: National Semiconductor

Specifications of ADC1001CCJ-1

• Number Of Bits: 10
• Sampling Rate (per Second): 4.6k
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-CDIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *ADC1001CCJ-1

www.national.com
Timing Diagrams
Byte Sequencing For The 20-Pin ADC1001
Functional Description
The ADC1001 uses an advanced potentiometric resistive
ladder network. The analog inputs, as well as the taps of this
ladder network, are switched into a weighted capacitor array.
The output of this capacitor array is the input to a sampled
data comparator. This comparator allows the successive ap-
proximation logic to match the analog difference input volt-
age [V
nificant bit is tested first and after 10 comparisons (80 clock
cycles) a digital 10-bit binary code (all “1”s = full-scale) is
transferred to an output latch and then an interrupt is as-
serted (INTR makes a high-to-low transition). The device
may be operated in the free-running mode by connecting
INTR to the WR input with CS = 0. To ensure start-up under
all possible conditions, an external WR pulse is required dur-
ing the first power-up cycle. A conversion in process can be
interrupted by issuing a second start command.
On the high-to-low transition of the WR input the internal
SAR latches and the shift register stages are reset. As long
as the CS input and WR input remain low, the A/D will remain
in a reset state. Conversion will start from 1 to 8 clock peri-
ods after at least one of these inputs makes a low-to-high
transition.
A functional diagram of the A/D converter is shown in Figure
3 . All of the inputs and outputs are shown and the major logic
control paths are drawn in heavier weight lines.
The conversion is initialized by taking CS and WR simulta-
neously low. This sets the start flip-flop (F/F) and the result-
ing “1” level resets the 8-bit shift register, resets the Interrupt
(INTR) F/F and inputs a “1” to the D flop, F/F1, which is at the
input end of the 10-bit shift register. Internal clock signals
then transfer this “1” to the Q output of F/F1. The AND gate,
G1, combines this “1” output with a clock signal to provide a
reset signal to the start F/F. If the set signal is no longer
present (either WR or CS is a “1”) the start F/F is reset and
the 10-bit shift register then can have the “1” clocked in,
which allows the conversion process to continue. If the set
signal were to still be present, this reset pulse would have no
effect and the 10-bit shift register would continue to be held
in the reset mode. This logic therefore allows for wide CS
and WR signals and the converter will start after at least one
of these signals returns high and the internal clocks again
provide a reset signal for the start F/F.
After the “1” is clocked through the 10-bit shift register (which
completes the SAR search) it causes the new digital word to
transfer to the TRI-STATE output latches. When this XFER
signal makes a high-to-low transition the one shot fires, set-
ting the INTR F/F. An inverting buffer then supplies the INTR
output signal.
Note that this SET control of the INTR F/F remains low for
aproximately 400 ns. If the data output is continuously en-
abled (CS and RD both held low), the INTR output will still
signal the end of the conversion (by a high-to-low transition),
1st
2nd
Order
Byte
IN
(+)−V
MSB
DB7
Bit 9
Bit 1
IN
(−)] to taps on the R network. The most sig-
Bit 8
Bit 0
DB6
LSB
(Continued)
DB5
Bit 7
0
8-Bit Data Bus Connection
DB4
Bit 6
0
DB3
Bit 5
0
Bit 4
DB2
6
0
because the SET input can control the Q output of the INTR
F/F even though the RESET input is constantly at a “1” level.
This INTR output will therefore stay low for the duration of
the SET signal.
When data is to be read, the combination of both CS and RD
being low will cause the INTR F/F to be reset and the
TRI-STATE output latches will be enabled.
Zero and Full-Scale Adjustment
Zero error can be adjusted as shown in Figure 1 . V
forced to +2.5 mV (+
justed until the digital output code changes from 00 0000
0000 to 00 0000 0001.
Full-scale is adjusted as shown in Figure 2 , with the V
input. With V
less 1
digital output code changes from 11 1111 1110 to 11 1111
1111.
Bit 3
DB1
1
0
⁄
2
LSBs (V
IN
DB0
Bit 2
(+) forced to the desired full-scale voltage
0
FS
−1
1
1
⁄
2
⁄
2
LSB) and the potentiometer is ad-
LSBs), V
REF
/2 is adjusted until the
IN
REF
(+) is
/2