ADC10154BIWM National Semiconductor, ADC10154BIWM Datasheet - Page 20

• Manufacturer Part Number: ADC10154BIWM
• Description: IC ADC 10BIT W/4-8 CH MX SO20
• Manufacturer: National Semiconductor

Specifications of ADC10154BIWM

• Number Of Bits: 10
• Sampling Rate (per Second): 166k
• Number Of Converters: 1
• Power Dissipation (max): 33mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -65°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *ADC10154BIWM

www.national.com
2.0 Applications Information
voltage which is necessary to just cause an output digital
code transition from 000 0000 0000 to 000 0000 0001
(10-bits plus sign) and the ideal
mV for V
The zero error of the A/D does not require adjustment. If the
minimum analog input voltage value, V
the effetive “zero” voltage can be adjusted to a convenient
value. The converter can be made to output an all zeros
digital code for this minimum input voltage by biasing any
minus input to V
tial or pseudo-differential input channel configurations.
2.4.2 Full-Scale
The full-scale adjustment can be made by applying a differ-
ential input voltage which is 1
analog full-scale voltage range and then adjusting the V
voltage (V
changing from 011 1111 1110 to 011 1111 1111. In bipolar
signed operation this only adjusts the positive full scale error.
The negative full-scale error will be as specified in the Elec-
trical Characteristics after a positive full-scale adjustment.
2.4.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
should be properly adjusted first. A plus input voltage which
equals this desired zero reference plus
LSB is calculated for the desired analog span, using 1 LSB =
analog span/2
plied to selected plus input and the zero reference voltage at
the corresponding minus input should then be adjusted to
just obtain the 000
The full-scale adjustment should be made [with the proper
minus input voltage applied] by forcing a voltage to the plus
input which is given by:
where V
V
and n equals the programmed resolution. Both V
V
voltage is then adjusted to provide a code change from
3FE
or differential multiplexer mode where V
placed within the V
V
analog input voltage span. This completes the adjustment
procedure.
2.5 INPUT SAMPLE-AND-HOLD
The ADC10154/8’s sample/hold capacitor is implemented in
the capacitor array. After the channel address is loaded, the
array is switched to sample the selected positive analog
input. The rising edge of WR loads the multiplexer address-
ing information. The sampling period for the assigned posi-
tive input is maintained for the duration of the acquisition
time (t
rising edge of WR.
(Continued)
MIN
MIN
REF
HEX
+
equals the low end (the offset zero) of the analog range
are ground referred. The V
A
and V
), i.e., approximately 6 to 8 clock cycles after the
MAX
to 3FF
REF
REF
equals the high end of the ananlog input range,
REF
= + 5.000V and 10-bit plus sign resolution).
n
= V
, n being the programmed resolution) is ap-
HEX
IN
−
(Min). This is useful for either the differen-
do not matter, only the difference sets the
HEX
REF
. Note, when using a pseudo-differential
+
and V
+
to 001
− V
−
REF
range, the individual values of
1
HEX
⁄
2
1
REF
−
⁄
LSB down from the desired
2
) for a digital output code
code transition.
LSB value (
(V
REF
IN
REF
(Min), is not ground,
1
⁄
2
= V
+
LSB (where the
and V
1
REF
⁄
2
LSB = 2.44
+
− V
REF
MAX
REF
− are
and
REF
−
)
20
An acquisition window of 6 clock cycles is available to allow
the voltage on the capacitor array to settle to the positive
analog input voltage. Any change in the analog voltage on a
selected positive input before or after the acquisition window
will not effect the A/D conversion result.
In the simplest case, the array’s acquisition time is deter-
mined by the R
stray input capacitance C
and stray (C
source resistance the analog input can be modeled as an
RC network as shown in Figure 6 . The values shown yield an
acquisition time of about 1.1 µs for 10-bit unipolar or 10-bit
plus sign bipolar accuracy with a zero-to-full-scale change in
the input voltage. External source resistance and capaci-
tance will lengthen the acquisition time and should be ac-
counted for. Slowing the clock will lengthen the acquisition
time, thereby allowing a larger external source resistance.
The curve “Signal to Noise Ratio vs. Output Frequency”
( Figure 7 ) gives an indication of the usable bandwidth of the
ADC10154/ADC10158. The signal-to-noise ratio of an ideal
A/D is the ratio of the RMS value of the full scale input signal
amplitude to the value of the total error amplitude (including
noise) caused by the transfer function of the A/D. An ideal
10-bit plus sign A/D converter with a total unadjusted error of
0 LSB would have a signal-to-noise ratio of about 68 dB,
which can be derived from the equation:
where S/N is in dB and n is the number of bits. Figure 3
shows the signal-to-noise ratio vs. input frequency of a typi-
cal ADC10154/ADC10158 with
ror. The dotted lines show signal-to-noise ratios for an ideal
(noiseless) 10-bit A/D with 0 LSB error and an A/D with a 1
LSB error.
Signal-to-Noise Ratio vs Input Frequency
S2
FIGURE 7. ADC10154/ADC10158
FIGURE 6. Analog Input Model
) capacitance (C
ON
SNR vs Input Frequency
S/N = 6.02(n) + 1.76
(9 k ) of the multiplexer switches, the
S1
(3.5 pF) and the total array (C
L
1
+ C
⁄
2
LSB total unadjusted er-
S2
= 48 pF). For a large
DS011225-24
DS011225-23
L
)