MAX188BEWP+T Maxim Integrated Products, MAX188BEWP+T Datasheet - Page 12

• Manufacturer Part Number: MAX188BEWP+T
• Description: IC ADC 12BIT SERIAL 20-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX188BEWP+T

• Resolution (bits): 12 b
• Sampling Rate (per Second): 133k
• Data Interface: Serial
• Voltage Supply Source: Dual ±
• Voltage - Supply: ±5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX186/MAX188 may use either an external serial
clock or the internal clock to perform the
successive-approximation conversion. In both clock
modes, the external clock shifts data in and out of the
MAX186/MAX188. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7 through 10 show the timing
characteristics common to both modes.
In external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-
Low-Power, 8-Channel,
Serial 12-Bit ADCs
Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)
Figure 7. Detailed Serial-Interface Timing
12
SSTRB
A/D STATE
DOUT
SCLK
DIN
CS
______________________________________________________________________________________
DOUT
SCLK
DIN
CS
Internal and External Clock Modes
START SEL2 SEL1 SEL0 UNI/
1
t
CSH
IDLE
t
RB1
DV
t
4
CSS
t
BIP
DS
1.5µs (CLK = 2MHz)
t
DH
SCL/
DIFF PD1 PD0
ACQUISITION
t
ACQ
8
External Clock
t
CL
t
MSB B10
B11
CH
B9
12
RB2
version steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive-approxi-
mation bit decisions are made and appear at DOUT on
each of the next 12 SCLK falling edges (see Figure 6).
SSTRB and DOUT go into a high-impedance state when
CS goes high; after the next CS falling edge, SSTRB will
output a logic low. Figure 8 shows the SSTRB timing in
external clock mode.
The conversion must complete in some minimum time, or
else droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if the
clock period exceeds 10µs, or if serial-clock interruptions
could cause the conversion interval to exceed 120µs.
B8
CONVERSION
B7
B6
B5
16
t
DO
B4
B3
B2
t
CSH
B1
20
RB3
LSB
B0
FILLED WITH
ZEROS
t
IDLE
TR
24