MAX188BEWP+T Maxim Integrated Products, MAX188BEWP+T Datasheet - Page 7

• Manufacturer Part Number: MAX188BEWP+T
• Description: IC ADC 12BIT SERIAL 20-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX188BEWP+T

• Resolution (bits): 12 b
• Sampling Rate (per Second): 133k
• Data Interface: Serial
• Voltage Supply Source: Dual ±
• Voltage - Supply: ±5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disabled Time
________________________________________________Pin Description (continued)
DOUT
PIN
12
13
14
15
16
17
18
19
20
a. High-Z to V
DOUT
3k
3k
OH
DGND
REFADJ
a V
SSTRB
NAME
AGND
DGND
DOUT
and V
SCLK
V
DIN
CS
OH
DGND
DD
_______________________________________________________________________________________
to High-Z
OL
to V
OH
C
LOAD
C
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to
V
Analog Ground. Also IN- Input for single-ended conversions.
Digital Ground
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the
A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CS is high (external mode).
Serial Data Input. Data is clocked in at the rising edge of SCLK.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
Positive Supply Voltage, +5V ±5%
LOAD
DD
b. High-Z to V
.
DOUT
DOUT
b V
+5V
+5V
OL
OL
to High-Z
and V
3k
C
DGND
LOAD
3k
C
DGND
LOAD
OH
to V
OL
Figure 3. Block Diagram
Low-Power, 8-Channel,
REFADJ
SHDN
AGND
SCLK
VREF
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
DIN
CS
FUNCTION
18
19
17
10
13
12
11
1
2
3
4
5
6
7
8
Serial 12-Bit ADCs
REGISTER
ANALOG
INPUT
SHIFT
INPUT
MUX
REFERENCE
(MAX186)
+2.46V
CONTROL
T/H
LOGIC
20k
A
+4.096V
IN
CLOCK
1.65
12-BIT
CLOCK
SAR
ADC
INT
REF
OUT
MAX186
MAX188
REGISTER
OUTPUT
SHIFT
20
14
9
15
16
DOUT
SSTRB
V
DGND
V
DD
SS
7