MCP4351-103E/ST Microchip Technology, MCP4351-103E/ST Datasheet - Page 48
Manufacturer Part Number
IC DGTL POT QUAD 10K 20TSSOP
Specifications of MCP4351-103E/ST
Number Of Circuits
150 ppm/°C Typical
Voltage - Supply
1.8 V ~ 5.5 V
-40°C ~ 125°C
Package / Case
Resistance In Ohms
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SDI, SDO, SCK, and CS Operation
The operation of the four SPI interface pins are
discussed in this section. These pins are:
• SDI (Serial Data In)
• SDO (Serial Data Out)
• SCK (Serial Clock)
• CS (Chip Select)
The serial interface works on either 8-bit or 16-bit
boundaries depending on the selected command. The
Chip Select (CS) pin frames the SPI commands.
SERIAL DATA IN (SDI)
The Serial Data In (SDI) signal is the data signal into
the device. The value on this pin is latched on the rising
edge of the SCK signal.
SERIAL DATA OUT (SDO)
The Serial Data Out (SDO) signal is the data signal out
of the device. The value on this pin is driven on the
falling edge of the SCK signal.
Once the CS pin is forced to the active level (V
), the SDO pin will be driven. The state of the SDO
pin is determined by the serial bit’s position in the
command, the command selected, and if there is a
command error state (CMDERR).
SERIAL CLOCK (SCK)
(SPI FREQUENCY OF OPERATION)
The SPI interface is specified to operate up to 10 MHz.
The actual clock rate depends on the configuration of
the system and the serial command used.
shows the SCK frequency.
Memory Type Access
This is the maximum clock frequency
without an external pull-up resistor.
THE CS SIGNAL
The Chip Select (CS) signal is used to select the device
and frame a command sequence. To start a command,
or sequence of commands, the CS signal must
transition from the inactive state (V
After the CS signal has gone active, the SDO pin is
driven and the clock bit counter is reset.
There is a required delay after the CS pin
goes active to the 1st edge of the SCK pin.
If an error condition occurs for an SPI command, then
the command byte’s Command Error (CMDERR) bit
(on the SDO pin) will be driven low (V
error condition, the user must take the CS pin to the V
When the CS pin returns to the inactive state (V
SPI module resets (including the Address Pointer).
While the CS pin is in the inactive state (V
interface is ignored. This allows the host controller to
interface to other SPI devices using the same SDI,
SDO and SCK signals.
The CS pin has an internal pull-up resistor. The resistor
is disabled when the voltage on the CS pin is at the V
level. This means that when the CS pin is not driven,
the internal pull-up resistor will pull this signal to the V
level. When the CS pin is driven low (V
resistance becomes very large to reduce the device
The high voltage capability of the CS pin allows High
commands allows circuit compatibility with the
corresponding nonvolatile device.
) to an active state
). To exit the
), the serial
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