CS4334-KSZ Cirrus Logic Inc, CS4334-KSZ Datasheet - Page 13

• Manufacturer Part Number: CS4334-KSZ
• Description: IC DAC STER 24BIT 96KHZ 8-SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4334-KSZ

• Package / Case: 8-SOIC
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 104mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 5 V
• Operating Temperature Range: + 70 C
• Maximum Power Dissipation: 104 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1510 - BOARD EVAL FOR CS4334 CODEC
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1046-5

DS248F5
4. SYSTEM DESIGN
The CS4334 family accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in BRM and 96, 88.2
and 64 kHz in HRM. Audio data is input via the serial data input pin (SDATA). The Left/Right Clock (LRCK) defines
the channel and delineation of data, and the Serial Clock (SCLK) clocks audio data into the input data buffer. The
CS4334/5/8/9 differ in serial data formats as shown in
4.1
4.2
4.2.1
4.2.2
Master Clock
MCLK must be either 256x, 384x or 512x the desired input sample rate in BRM and either 128x or 192x the
desired input sample rate in HRM. The LRCK frequency is equal to Fs, the frequency at which words for
each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected automatically during
the initialization sequence by counting the number of MCLK transitions during a single LRCK period. Internal
dividers are set to generate the proper clocks.
the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK,
LRCK and SCLK must be synchronous.
Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4334 family supports both
external and internal serial clock generation modes. Refer to
External Serial Clock Mode
The CS4334 family will enter the External Serial Clock Mode when 16 low to high transitions are detected
on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Se-
rial Clock Mode and de-emphasis filter cannot be accessed. The CS4334 family will switch to Internal Se-
rial Clock Mode if no low to high transitions are detected on the DEM/SCLK pin for 2 consecutive frames
of LRCK. Refer to
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and
LRCK. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon data format. Operation in
this mode is identical to operation with an external serial clock synchronized with LRCK. This mode allows
access to the digital de-emphasis function. Refer to
Figure
LRCK
(kHz)
44.1
88.2
32
48
64
96
14.
Table 1. Common Clock Frequencies
12.2880 18.4320
11.2896 16.9344
4.0960
5.6448
6.1440
8.1920 12.2880
128x
HRM
Confidential Draft
6.1440
8.4672 11.2896 16.9344 22.5792
9.2160 12.2880 18.4320 24.5760
192x
3/11/08
Figures
MCLK (MHz)
Table 1
8.1920 12.2880 16.3840
256x
-
-
-
Figures 10
10-13.
illustrates several standard audio sample rates and
BRM
384x
Figures 10-13
-
-
-
-
14
512x
for details.
-
-
-
for data formats.
CS4334/5/8/9
13