CS4334-KSZ Cirrus Logic Inc, CS4334-KSZ Datasheet - Page 15

• Manufacturer Part Number: CS4334-KSZ
• Description: IC DAC STER 24BIT 96KHZ 8-SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4334-KSZ

• Package / Case: 8-SOIC
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 104mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 5 V
• Operating Temperature Range: + 70 C
• Maximum Power Dissipation: 104 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1510 - BOARD EVAL FOR CS4334 CODEC
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1046-5

DS248F5
4.6
4.7
S D A T A
S D A T A
I²S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128
I²S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
LR C K
LR C K
S C L K
S C L K
down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the
time that the device must remain in the power-down state will be approximately 0.4 seconds.
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4334 family requires careful attention to power supply and
grounding arrangements to optimize performance. Figure
with VA connected to a clean +5V supply. For best performance, decoupling capacitors should be located
as close to the device package as possible with the smallest capacitor closest.
Analog Output and Filtering
The analog filter present in the CS4334 family is a switched-capacitor filter followed by a continuous time
low pass filter. Its response, combined with that of the digital interpolator, is given in
MSB -1 -2 -3 -4 -5
M SB -1 -2 -3 -4 -5
Internal SCLK Mode
Internal SCLK Mode
Le ft C ha n nel
+5 +4
Le ft C ha n nel
+5 +4
+3 +2 +1 LSB
+3 +2 +1 LS B
Figure 10. CS4334 Data Format (I²S)
Figure 11. CS4335 Data Format
Confidential Draft
3/11/08
I²S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
M SB -1 -2 -3 -4
MSB -1 -2 -3 -4
1
shows the recommended power arrangement
External SCLK Mode
External SCLK Mode
+5 +4
+5 +4
R ig h t C ha n nel
R ig h t C ha n nel
+3 +2 +1 LSB
+3 +2 +1 LS B
Figures 15
CS4334/5/8/9
- 22.
15