AD9740ARURL7 Analog Devices Inc, AD9740ARURL7 Datasheet - Page 15

• Manufacturer Part Number: AD9740ARURL7
• Description: IC DAC 10BIT 210MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9740ARURL7

• Rohs Status: RoHS non-compliant
• Settling Time: 11ns
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 145mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• For Use With: AD9740ACP-PCBZ - BOARD EVAL FOR AD9740ACP

transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed
waveform increases and/or its amplitude decreases. This is due
to the first-order cancellation of various dynamic common-
mode distortion mechanisms, digital feedthrough, and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (assuming no source
termination). Because the output currents of IOUTA and
IOUTB are complementary, they become additive when
processed differentially. A properly selected transformer allows
the AD9740 to provide the required power and voltage levels to
different loads.
The output impedance of IOUTA and IOUTB is determined by
the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, V
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration results in the
optimum dc linearity. Note that the INL/DNL specifications for
the AD9740 are measured with IOUTA maintained at a virtual
ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit can result in a
breakdown of the output stage and affect the reliability of the
AD9740.
The positive output compliance range is slightly dependent on
the full-scale output current, I
nominal 1.2 V for an I
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9740 digital section consists of 10 input bit channels
and a clock input. The 10-bit parallel data inputs follow
standard positive binary coding, where DB9 is the most
significant bit (MSB) and DB0 is the least significant bit (LSB).
IOUTA produces a full-scale output current when all data bits
are at Logic 1. IOUTB produces a complementary output with
the full-scale current split between the two outputs as a
function of the input code.
OUTA
and V
OUTFS
= 20 mA to 1 V for an I
OUTB
OUTFS
) due to the nature of a PMOS
. It degrades slightly from its
OUTFS
= 2 mA.
Rev. B | Page 15 of 32
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
210 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges can affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
CLOCK INPUT
SOIC/TSSOP Packages
The 28-lead package options have a single-ended clock input
(CLOCK) that must be driven to rail-to-rail CMOS levels. The
quality of the DAC output is directly related to the clock quality,
and jitter is a key concern. Any noise or jitter in the clock
translates directly into the DAC output. Optimal performance is
achieved if the CLOCK input has a sharp rising edge, because
the DAC latches are positive edge triggered.
LFCSP Package
A configurable clock input is available in the LFCSP package,
which allows for one single-ended and two differential modes.
The mode selection is controlled by the CMODE input, as
summarized in Table 6. Connecting CMODE to CLKCOM
selects the single-ended clock input. In this mode, the CLK+
input is driven with rail-to-rail swings and the CLK− input is
left floating. If CMODE is connected to CLKVDD, then the
differential receiver mode is selected. In this mode, both inputs
are high impedance. The final mode is selected by floating
CMODE. This mode is also differential, but internal
terminations for positive emitter-coupled logic (PECL) are
activated. There is no significant performance difference
between any of the three clock input modes.
Table 6. Clock Mode Selection
CMODE Pin
CLKCOM
CLKVDD
Float
The single-ended input mode operates in the same way as the
clock input in the 28-lead packages, as described previously.
DIGITAL
INPUT
Figure 26. Equivalent Digital Input
Clock Input Mode
Single-ended
Differential
PECL
DVDD
AD9740