AD9740ARU Analog Devices Inc, AD9740ARU Datasheet - Page 16

• Manufacturer Part Number: AD9740ARU
• Description: IC DAC 10BIT 210MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9740ARU

• Rohs Status: RoHS non-compliant
• Settling Time: 11ns
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 145mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• For Use With: AD9740ACP-PCBZ - BOARD EVAL FOR AD9740ACP

AD9740
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave
because the high gain bandwidth of the differential inputs
converts the sine wave into a single-ended square wave internally.
The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 27. These termination resistors are untrimmed and can
vary up to ±20%. However, matching between the resistors
should generally be better than ±1%.
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the
relationship between the position of the clock edges and the
time at which the input data changes. The AD9740 is rising
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the
goal when applying the AD9740 is to make the data transition
close to the falling clock edge. This becomes more important as
the sample rate increases. Figure 28 shows the relationship of
SFDR to clock placement with different sample rates. Note that
at the lower sample rates, more tolerance is allowed in clock
placement, while at higher rates, more care must be taken.
CLK+
CLK–
50Ω
Figure 27. Clock Termination in PECL Mode
V
TT
= 1.3V NOM
50Ω
CLOCK
RECEIVER
AD9740
TO DAC CORE
Rev. B | Page 16 of 32
Sleep Mode Operation
The AD9740 has a power-down function that turns off the output
current and reduces the supply current to less than 6 mA over the
specified supply range of 2.7 V to 3.6 V and the temperature range.
This mode can be activated by applying a Logic Level 1 to the
SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω
AVDD. This digital input also contains an active pull-down
circuit that ensures that the AD9740 remains enabled if this
input is left disconnected. The AD9740 takes less than 50 ns
to power down and approximately 5 μs to power back up.
POWER DISSIPATION
The power dissipation, P
several factors that include:
•
•
•
•
The power dissipation is directly proportional to the analog
supply current, I
is directly proportional to I
insensitive to f
digital input waveform, f
shows I
(f
OUT
75
70
65
60
55
50
45
40
35
The power supply voltages (AVDD, CLKVDD, and
DVDD)
The full-scale current output (I
The update rate (f
The reconstructed digital input waveform
/f
–3
CLOCK
50MHz SFDR
DVDD
) for various update rates with DVDD = 3.3 V.
as a function of full-scale sine wave output ratios
f
OUT
–2
CLOCK
Figure 28. SFDR vs. Clock Placement @
AVDD
= 20 MHz and 50 MHz (f
. Conversely, I
, and the digital supply current, I
20MHz SFDR
CLOCK
CLOCK
–1
D
, of the AD9740 is dependent on
OUTFS
)
, and digital supply DVDD. Figure 30
, as shown in Figure 29, and is
ns
0
DVDD
OUTFS
CLOCK
is dependent on both the
50MHz SFDR
)
= 165 MSPS)
1
2
DVDD
. I
AVDD
3